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libTriton version 1.0 build 1599
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[internal] List of the supported semantics for the AArch64 architecture.
| Mnemonic | Description |
|---|---|
| ADC | Add with Carry |
| ADCS | Add with Carry, setting flags |
| ADD (extended register) | Add (extended register) |
| ADD (immediate) | Add (immediate) |
| ADD (shifted register) | Add (shifted register) |
| ADDS (extended register) | Add (extended register), setting flags |
| ADDS (immediate) | Add (immediate), setting flags |
| ADDS (shifted register) | Add (shifted register), setting flags |
| ADR | Form PC-relative address |
| ADRP | Form PC-relative address to 4KB page |
| AND (immediate) | Bitwise AND (immediate) |
| AND (shifted register) | Bitwise AND (shifted register) |
| ANDS (immediate) | Bitwise AND (immediate), setting flags |
| ANDS (shifted register) | Bitwise AND (shifted register), setting flags |
| ASR (immediate) | Arithmetic Shift Right (immediate): an alias of SBFM |
| ASR (register) | Arithmetic Shift Right (register): an alias of ASRV |
| B | Branch |
| BFI | Bit Field Insert |
| BFXIL | Bitfield extract and insert at low end: an alias of BFM |
| BIC | Bitwise Bit Clear |
| BICS | Bitwise Bit Clear, setting flags |
| BL | Branch with Link |
| BLR | Branch with Link to Register |
| BR | Branch to Register |
| BRK | Breakpoint instruction |
| CBNZ | Compare and Branch on Nonzero |
| CBZ | Compare and Branch on Zero |
| CCMP (immediate) | Conditional Compare (immediate) |
| CCMP (register) | Conditional Compare (register) |
| CINC | Conditional Increment: an alias of CSINC |
| CLZ | Count Leading Zeros |
| CMN (extended register) | Compare Negative (extended register): an alias of ADDS (extended register) |
| CMN (immediate) | Compare Negative (immediate): an alias of ADDS (immediate) |
| CMN (shifted register) | Compare Negative (shifted register): an alias of ADDS (shifted register) |
| CMP (extended register) | Compare (extended register): an alias of SUBS (extended register) |
| CMP (immediate) | Compare (immediate): an alias of SUBS (immediate) |
| CMP (shifted register) | Compare (shifted register): an alias of SUBS (shifted register) |
| CNEG | Conditional Negate returns: an alias of CSNEG |
| CSEL | Conditional Select |
| CSET | Conditional Set: an alias of CSINC |
| CSINC | Conditional Select Increment |
| CSINV | Conditional Select Inversion |
| CSNEG | Conditional Select Negation |
| EON (shifted register) | Bitwise Exclusive OR NOT (shifted register) |
| EOR (immediate) | Bitwise Exclusive OR (immediate) |
| EOR (shifted register) | Bitwise Exclusive OR (shifted register) |
| EXTR | EXTR: Extract register |
| FMOV | Floating-point Move register without conversion. |
| LD3 (multiple structure) | Load multiple 3-element structures to three registers. |
| LD3R | Load single 3-element structure and Replicate to all lanes of three registers. |
| LD4 (multiple structure) | Load multiple 4-element structures to four registers. |
| LD4R | Load single 4-element structure and Replicate to all lanes of four registers. |
| LDAR | Load-Acquire Register |
| LDARB | Load-Acquire Register Byte |
| LDARH | Load-Acquire Register Halfword |
| LDAXR | Load-Acquire Exclusive Register |
| LDAXRB | Load-Acquire Exclusive Register Byte |
| LDAXRH | Load-Acquire Exclusive Register Halfword |
| LDNP | Load Pair of Registers with non-temporal hint |
| LDP | Load Pair of Registers |
| LDPSW | Load Pair of Registers Signed Word |
| LDR (immediate) | Load Register (immediate) |
| LDR (literal) | Load Register (literal) |
| LDR (register) | Load Register (register) |
| LDRB (immediate) | Load Register Byte (immediate) |
| LDRB (register) | Load Register Byte (register) |
| LDRH (immediate) | Load Register Halfword (immediate) |
| LDRH (register) | Load Register Halfword (register) |
| LDRSB (immediate) | Load Register Signed Byte (immediate) |
| LDRSB (register) | Load Register Signed Byte (register) |
| LDRSH (immediate) | Load Register Signed Halfword (immediate) |
| LDRSH (register) | Load Register Signed Halfword (register) |
| LDRSW (immediate) | Load Register Signed Word (immediate) |
| LDRSW (literal) | Load Register Signed Word (literal) |
| LDRSW (register) | Load Register Signed Word (register) |
| LDTR | Load Register (unprivileged) |
| LDTRB | Load Register Byte (unprivileged) |
| LDTRH | Load Register Halfword (unprivileged) |
| LDTRSB | Load Register Signed Byte (unprivileged) |
| LDTRSH | Load Register Signed Halfword (unprivileged) |
| LDTRSW | Load Register Signed Word (unprivileged) |
| LDUR | Load Register (unscaled) |
| LDURB | Load Register Byte (unscaled) |
| LDURH | Load Register Halfword (unscaled) |
| LDURSB | Load Register Signed Byte (unscaled) |
| LDURSH | Load Register Signed Halfword (unscaled) |
| LDURSW | Load Register Signed Word (unscaled) |
| LDXP | Load Exclusive Pair of Registers |
| LDXR | Load Exclusive Register |
| LDXRB | Load Exclusive Register Byte |
| LDXRH | Load Exclusive Register Halfword |
| LSL (immediate) | Logical Shift Left (immediate): an alias of UBFM |
| LSL (register) | Logical Shift Left (register): an alias of LSLV |
| LSR (immediate) | Logical Shift Right (immediate): an alias of UBFM |
| LSR (register) | Logical Shift Right (register): an alias of LSRV |
| MADD | Multiply-Add |
| MNEG | Multiply-Negate: an alias of MSUB |
| MOV (bitmask immediate) | Move (bitmask immediate): an alias of ORR (immediate) |
| MOV (register) | Move (register): an alias of ORR (shifted register) |
| MOV (to/from SP) | Move between register and stack pointer: an alias of ADD (immediate) |
| MOVI | Move Immediate (vector) |
| MOVK | Move wide with keep |
| MOVN | Move wide with NOT |
| MOVZ | Move shifted 16-bit immediate to register |
| MRS | Move System Register to general-purpose register |
| MSR | Move general-purpose register to System Register |
| MSUB | Multiply-Subtract |
| MUL | Multiply: an alias of MADD |
| MVN | Bitwise NOT: an alias of ORN (shifted register) |
| NEG (shifted register) | Negate (shifted register): an alias of SUB (shifted register) |
| NOP | No Operation |
| ORN | Bitwise OR NOT (shifted register) |
| ORR (immediate) | Bitwise OR (immediate) |
| ORR (shifted register) | Bitwise OR (shifted register) |
| RBIT | Reverse Bits |
| RET | Return from subroutine |
| REV | Reverse Bytes |
| REV16 | Reverse bytes in 16-bit halfwords |
| REV32 | Reverse bytes in 32-bit words |
| REV64 | Reverse Bytes: an alias of REV |
| ROR (immediate) | Rotate right (immediate): an alias of EXTR |
| ROR (register) | Rotate Right (register): an alias of RORV |
| RORV | Rotate Right Variable |
| SBC | Subtract with Carry |
| SBCS | Subtract with Carry, setting flags |
| SBFX | Signed Bitfield Extract: an alias of SBFM |
| SDIV | Signed Divide |
| SMADDL | Signed Multiply-Add Long |
| SMSUBL | Signed Multiply-Subtract Long |
| SMULH | Signed Multiply High |
| SMULL | Signed Multiply Long: an alias of SMADDL |
| STLR | Store-Release Register |
| STLRB | Store-Release Register Byte |
| STLRH | Store-Release Register Halfword |
| STLXR | Store-Release Exclusive Register |
| STLXRB | Store-Release Exclusive Register Byte |
| STLXRH | Store-Release Exclusive Register Halfword |
| STNP | Store Pair of Registers with non-temporal hint |
| STP | Store Pair of Registers |
| STR (immediate) | Store Register (immediate) |
| STR (register) | Store Register (register) |
| STRB (immediate) | Store Register Byte (immediate) |
| STRB (register) | Store Register Byte (register) |
| STRH (immediate) | Store Register Halfword (immediate) |
| STRH (register) | Store Register Halfword (register) |
| STTR | Store Register (unprivileged) |
| STTRB | Store Register Byte (unprivileged) |
| STTRH | Store Register Halfword (unprivileged) |
| STUR | Store Register (unscaled) |
| STURB | Store Register Byte (unscaled) |
| STURH | Store Register Halfword (unscaled) |
| STXP | Store Exclusive Pair or Registers |
| STXR | Store Exclusive Register |
| STXRB | Store Exclusive Register Byte |
| STXRH | Store Exclusive Register Halfword |
| SUB (extended register) | Subtract (extended register) |
| SUB (immediate) | Subtract (immediate) |
| SUB (shifted register) | Subtract (shifted register) |
| SUBS (extended register) | Subtract (extended register), setting flags |
| SUBS (immediate) | Subtract (immediate), setting flags |
| SUBS (shifted register) | Subtract (shifted register), setting flags |
| SVC | Supervisor Call |
| SXTB | Signed Extend Byte: an alias of SBFM |
| SXTH | Sign Extend Halfword: an alias of SBFM |
| SXTW | Sign Extend Word: an alias of SBFM |
| TBNZ | Test bit and Branch if Nonzero |
| TBZ | Test bit and Branch if Zero |
| TST (immediate) | Test bits (immediate): an alias of ANDS (immediate) |
| TST (shifted register) | Test (shifted register): an alias of ANDS (shifted register) |
| UBFIZ | Unsigned Bitfield Insert in Zero: an alias of UBFM |
| UBFX | Unsigned Bitfield Extract: an alias of UBFM |
| UDIV | Unsigned Divide |
| UMADDL | Unsigned Multiply-Add Long |
| UMNEGL | Unsigned Multiply-Negate Long: an alias of UMSUBL |
| UMOV | Unsigned Move vector element to GPR |
| UMSUBL | Unsigned Multiply-Subtract Long |
| UMULH | Unsigned Multiply High |
| UMULL | Unsigned Multiply Long: an alias of UMADDL |
| UXTB | Unsigned Extend Byte: an alias of UBFM |
| UXTH | Unsigned Extend Halfword: an alias of UBFM |
1.10.0