|
#define | REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, X86_AVAIL) |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, _8) xPyDict_SetItemString(x8664RegistersDict, #UPPER_NAME, PyLong_FromUint32(triton::arch::ID_REG_X86_##UPPER_NAME)); |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) xPyDict_SetItemString(aarch64RegistersDict, #UPPER_NAME, PyLong_FromUint32(triton::arch::ID_REG_AARCH64_##UPPER_NAME)); |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | SYS_REG_SPEC REG_SPEC |
|
#define | REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) xPyDict_SetItemString(arm32RegistersDict, #UPPER_NAME, PyLong_FromUint32(triton::arch::ID_REG_ARM32_##UPPER_NAME)); |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | REG_SPEC(_0, UPPER_NAME, _1, _2, _3, _4, _5) xPyDict_SetItemString(riscv64RegistersDict, #UPPER_NAME, PyLong_FromUint32(triton::arch::ID_REG_RV64_##UPPER_NAME)); |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | SYS_REG_SPEC REG_SPEC |
|
#define | REG_SPEC(_0, UPPER_NAME, _1, _2, _3, _4, _5) xPyDict_SetItemString(riscv32RegistersDict, #UPPER_NAME, PyLong_FromUint32(triton::arch::ID_REG_RV32_##UPPER_NAME)); |
|
#define | REG_SPEC_NO_CAPSTONE REG_SPEC |
|
#define | SYS_REG_SPEC REG_SPEC |
|