archEnums.hpp

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/*
**  Copyright (C) - Triton
**
**  This program is under the terms of the Apache License 2.0.
*/
 
#ifndef TRITON_ARCHENUMS_HPP
#define TRITON_ARCHENUMS_HPP
 
#include <cstdint>
#include <functional>
 
 
 
namespace triton {
  namespace arch {
    enum architecture_e {
      ARCH_INVALID = 0, 
      ARCH_AARCH64,     
      ARCH_ARM32,       
      #ifdef COMPILE_RISCV
      ARCH_RV32,        
      ARCH_RV64,        
      #endif
      ARCH_X86,         
      ARCH_X86_64,      
    };
    enum architecture_e {…};
 
    enum endianness_e {
      LE_ENDIANNESS,    
      BE_ENDIANNESS,    
    };
    enum endianness_e {…};
 
    enum operand_e {
      OP_INVALID = 0,   
      OP_IMM,           
      OP_MEM,           
      OP_REG            
    };
    enum operand_e {…};
 
    enum exception_e {
      NO_FAULT = 0,     
      FAULT_DE,         
      FAULT_BP,         
      FAULT_UD,         
      FAULT_GP,         
    };
    enum exception_e {…};
 
    enum register_e {
      ID_REG_INVALID = 0, 
 
      #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, _8) \
      ID_REG_X86_##UPPER_NAME,
      #define REG_SPEC_NO_CAPSTONE REG_SPEC
      #include "triton/x86.spec"
 
      #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \
      ID_REG_AARCH64_##UPPER_NAME,
      #define REG_SPEC_NO_CAPSTONE REG_SPEC
      #define SYS_REG_SPEC REG_SPEC
      #include "triton/aarch64.spec"
 
      #define REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) \
      ID_REG_ARM32_##UPPER_NAME,
      #define REG_SPEC_NO_CAPSTONE REG_SPEC
      #include "triton/arm32.spec"
 
      #ifdef COMPILE_RISCV
      #define REG_SPEC(_1, UPPER_NAME, _2, _3, _4, _5, _6) \
      ID_REG_RV64_##UPPER_NAME,
      #define REG_SPEC_NO_CAPSTONE REG_SPEC
      #include "triton/riscv64.spec"
 
      #define REG_SPEC(_1, UPPER_NAME, _2, _3, _4, _5, _6) \
      ID_REG_RV32_##UPPER_NAME,
      #define REG_SPEC_NO_CAPSTONE REG_SPEC
      #include "triton/riscv32.spec"
      #endif
 
      /* Must be the last item */
      ID_REG_LAST_ITEM 
    };
    enum register_e {…};
 
    namespace x86 {
      enum prefix_e {
        ID_PREFIX_INVALID = 0,  
        ID_PREFIX_LOCK,         
        ID_PREFIX_REP,          
        ID_PREFIX_REPE,         
        ID_PREFIX_REPNE,        
 
        /* Must be the last item */
        ID_PREFIX_LAST_ITEM     
      };
      enum prefix_e {…};
 
    };
 
    namespace arm {
      enum shift_e {
        ID_SHIFT_INVALID = 0, 
        ID_SHIFT_ASR,         
        ID_SHIFT_LSL,         
        ID_SHIFT_LSR,         
        ID_SHIFT_ROR,         
        ID_SHIFT_RRX,         
        ID_SHIFT_ASR_REG,     
        ID_SHIFT_LSL_REG,     
        ID_SHIFT_LSR_REG,     
        ID_SHIFT_ROR_REG,     
        ID_SHIFT_RRX_REG,     
        ID_SHIFT_LAST_ITEM,   
      };
      enum shift_e {…};
 
      enum extend_e {
        ID_EXTEND_INVALID = 0,   
        ID_EXTEND_UXTB,          
        ID_EXTEND_UXTH,          
        ID_EXTEND_UXTW,          
        ID_EXTEND_UXTX,          
        ID_EXTEND_SXTB,          
        ID_EXTEND_SXTH,          
        ID_EXTEND_SXTW,          
        ID_EXTEND_SXTX,          
        ID_EXTEND_LAST_ITEM,     
      };
      enum extend_e {…};
 
      enum condition_e {
        ID_CONDITION_INVALID = 0, 
        ID_CONDITION_AL,          
        ID_CONDITION_EQ,          
        ID_CONDITION_GE,          
        ID_CONDITION_GT,          
        ID_CONDITION_HI,          
        ID_CONDITION_HS,          
        ID_CONDITION_LE,          
        ID_CONDITION_LO,          
        ID_CONDITION_LS,          
        ID_CONDITION_LT,          
        ID_CONDITION_MI,          
        ID_CONDITION_NE,          
        ID_CONDITION_PL,          
        ID_CONDITION_VC,          
        ID_CONDITION_VS,          
        ID_CONDITION_LAST_ITEM,   
      };
      enum condition_e {…};
 
      enum vas_e {
        ID_VAS_INVALID = 0, 
        ID_VAS_16B,         
        ID_VAS_8B,          
        ID_VAS_4B,          
        ID_VAS_1B,          
        ID_VAS_8H,          
        ID_VAS_4H,          
        ID_VAS_2H,          
        ID_VAS_1H,          
        ID_VAS_4S,          
        ID_VAS_2S,          
        ID_VAS_1S,          
        ID_VAS_2D,          
        ID_VAS_1D,          
        ID_VAS_1Q,          
        ID_VAS_LAST_ITEM,   
      };
      enum vas_e {…};
 
    };
 
    #ifdef COMPILE_RISCV
    namespace riscv {
      enum insn_group_e {
        ID_GRP_INVALID = 0,      
        /* Generic groups */
        ID_GRP_JUMP,             
        ID_GRP_CALL,             
        ID_GRP_RET,              
        ID_GRP_INT,              
        ID_GRP_IRET,             
        ID_GRP_PRIVILEGE,        
        ID_GRP_BRANCH_RELATIVE,  
        /* Architecture-specific groups */
        ID_GRP_ISRV32,
        ID_GRP_ISRV64,
        ID_GRP_HASSTDEXTA,
        ID_GRP_HASSTDEXTC,
        ID_GRP_HASSTDEXTD,
        ID_GRP_HASSTDEXTF,
        ID_GRP_HASSTDEXTM,
        /*
        ID_GRP_ISRVA,
        ID_GRP_ISRVC,
        ID_GRP_ISRVD,
        ID_GRP_ISRVCD,
        ID_GRP_ISRVF,
        ID_GRP_ISRV32C,
        ID_GRP_ISRV32CF,
        ID_GRP_ISRVM,
        ID_GRP_ISRV64A,
        ID_GRP_ISRV64C,
        ID_GRP_ISRV64D,
        ID_GRP_ISRV64F,
        ID_GRP_ISRV64M,
        */
 
        /* Must be the last item */
        ID_GRP_ENDING            
      };
 
    };
    #endif
  };
};
 
namespace std {
  template <> struct hash<triton::arch::register_e> : public hash<uint64_t> {
  };
  template <> struct hash<triton::arch::register_e> : public hash<uint64_t> {…};
};
 
#endif /* TRITON_ARCHENUMS_HPP */