#include <cstdint>
#include <functional>
#include "triton/x86.spec"
#include "triton/aarch64.spec"
#include "triton/arm32.spec"
#include "triton/riscv64.spec"
#include "triton/riscv32.spec"

This graph shows which files directly or indirectly include this file:

Classes
struct	std::hash< triton::arch::register_e >
	Define the hash function for register_e to be use in stl containers like unordered_map. More...

Namespaces
namespace	triton
	The Triton namespace.

namespace	triton::arch
	The Architecture namespace.

namespace	triton::arch::x86
	The x86 namespace.

namespace	triton::arch::arm
	The ARM namespace.

namespace	triton::arch::riscv
	The riscv namespace.

Macros
#define	REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5, _6, _7, _8) ID_REG_X86_##UPPER_NAME,

#define	REG_SPEC_NO_CAPSTONE REG_SPEC

#define	REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) ID_REG_AARCH64_##UPPER_NAME,

#define	REG_SPEC_NO_CAPSTONE REG_SPEC

#define	SYS_REG_SPEC REG_SPEC

#define	REG_SPEC(UPPER_NAME, _1, _2, _3, _4, _5) ID_REG_ARM32_##UPPER_NAME,

#define	REG_SPEC_NO_CAPSTONE REG_SPEC

#define	REG_SPEC(_1, UPPER_NAME, _2, _3, _4, _5, _6) ID_REG_RV64_##UPPER_NAME,

#define	REG_SPEC_NO_CAPSTONE REG_SPEC

#define	REG_SPEC(_1, UPPER_NAME, _2, _3, _4, _5, _6) ID_REG_RV32_##UPPER_NAME,

#define	REG_SPEC_NO_CAPSTONE REG_SPEC

Enumerations
enum	triton::arch::architecture_e { triton::arch::ARCH_INVALID = 0 , triton::arch::ARCH_AARCH64 , triton::arch::ARCH_ARM32 , triton::arch::ARCH_RV32 , triton::arch::ARCH_RV64 , triton::arch::ARCH_X86 , triton::arch::ARCH_X86_64 }

enum	triton::arch::endianness_e { triton::arch::LE_ENDIANNESS , triton::arch::BE_ENDIANNESS }

enum	triton::arch::operand_e { triton::arch::OP_INVALID = 0 , triton::arch::OP_IMM , triton::arch::OP_MEM , triton::arch::OP_REG }

enum	triton::arch::exception_e { triton::arch::NO_FAULT = 0 , triton::arch::FAULT_DE , triton::arch::FAULT_BP , triton::arch::FAULT_UD , triton::arch::FAULT_GP }

enum	triton::arch::register_e { triton::arch::ID_REG_INVALID = 0 , triton::arch::ID_REG_LAST_ITEM }
	Types of register. More...

enum	triton::arch::x86::prefix_e { triton::arch::x86::ID_PREFIX_INVALID = 0 , triton::arch::x86::ID_PREFIX_LOCK , triton::arch::x86::ID_PREFIX_REP , triton::arch::x86::ID_PREFIX_REPE , triton::arch::x86::ID_PREFIX_REPNE , triton::arch::x86::ID_PREFIX_LAST_ITEM }
	Types of prefix. More...

enum	triton::arch::arm::shift_e { triton::arch::arm::ID_SHIFT_INVALID = 0 , triton::arch::arm::ID_SHIFT_ASR , triton::arch::arm::ID_SHIFT_LSL , triton::arch::arm::ID_SHIFT_LSR , triton::arch::arm::ID_SHIFT_ROR , triton::arch::arm::ID_SHIFT_RRX , triton::arch::arm::ID_SHIFT_ASR_REG , triton::arch::arm::ID_SHIFT_LSL_REG , triton::arch::arm::ID_SHIFT_LSR_REG , triton::arch::arm::ID_SHIFT_ROR_REG , triton::arch::arm::ID_SHIFT_RRX_REG , triton::arch::arm::ID_SHIFT_LAST_ITEM }
	Types of shift. More...

enum	triton::arch::arm::extend_e { triton::arch::arm::ID_EXTEND_INVALID = 0 , triton::arch::arm::ID_EXTEND_UXTB , triton::arch::arm::ID_EXTEND_UXTH , triton::arch::arm::ID_EXTEND_UXTW , triton::arch::arm::ID_EXTEND_UXTX , triton::arch::arm::ID_EXTEND_SXTB , triton::arch::arm::ID_EXTEND_SXTH , triton::arch::arm::ID_EXTEND_SXTW , triton::arch::arm::ID_EXTEND_SXTX , triton::arch::arm::ID_EXTEND_LAST_ITEM }
	Types of extend. More...

enum	triton::arch::arm::condition_e { triton::arch::arm::ID_CONDITION_INVALID = 0 , triton::arch::arm::ID_CONDITION_AL , triton::arch::arm::ID_CONDITION_EQ , triton::arch::arm::ID_CONDITION_GE , triton::arch::arm::ID_CONDITION_GT , triton::arch::arm::ID_CONDITION_HI , triton::arch::arm::ID_CONDITION_HS , triton::arch::arm::ID_CONDITION_LE , triton::arch::arm::ID_CONDITION_LO , triton::arch::arm::ID_CONDITION_LS , triton::arch::arm::ID_CONDITION_LT , triton::arch::arm::ID_CONDITION_MI , triton::arch::arm::ID_CONDITION_NE , triton::arch::arm::ID_CONDITION_PL , triton::arch::arm::ID_CONDITION_VC , triton::arch::arm::ID_CONDITION_VS , triton::arch::arm::ID_CONDITION_LAST_ITEM }
	Types of condition. More...

enum	triton::arch::arm::vas_e { triton::arch::arm::ID_VAS_INVALID = 0 , triton::arch::arm::ID_VAS_16B , triton::arch::arm::ID_VAS_8B , triton::arch::arm::ID_VAS_4B , triton::arch::arm::ID_VAS_1B , triton::arch::arm::ID_VAS_8H , triton::arch::arm::ID_VAS_4H , triton::arch::arm::ID_VAS_2H , triton::arch::arm::ID_VAS_1H , triton::arch::arm::ID_VAS_4S , triton::arch::arm::ID_VAS_2S , triton::arch::arm::ID_VAS_1S , triton::arch::arm::ID_VAS_2D , triton::arch::arm::ID_VAS_1D , triton::arch::arm::ID_VAS_1Q , triton::arch::arm::ID_VAS_LAST_ITEM }
	Vector arrangement specifier. More...

enum	triton::arch::riscv::insn_group_e { triton::arch::riscv::ID_GRP_INVALID = 0 , triton::arch::riscv::ID_GRP_JUMP , triton::arch::riscv::ID_GRP_CALL , triton::arch::riscv::ID_GRP_RET , triton::arch::riscv::ID_GRP_INT , triton::arch::riscv::ID_GRP_IRET , triton::arch::riscv::ID_GRP_PRIVILEGE , triton::arch::riscv::ID_GRP_BRANCH_RELATIVE , ID_GRP_ISRV32 , ID_GRP_ISRV64 , ID_GRP_HASSTDEXTA , ID_GRP_HASSTDEXTC , ID_GRP_HASSTDEXTD , ID_GRP_HASSTDEXTF , ID_GRP_HASSTDEXTM , triton::arch::riscv::ID_GRP_ENDING }
	Groups of RISCV instructions. *‍/. More...

Macro Definition Documentation

◆ REG_SPEC [1/5]

#define REG_SPEC	(	_1,
		UPPER_NAME,
		_2,
		_3,
		_4,
		_5,
		_6 ) ID_REG_RV64_##UPPER_NAME,

Definition at line 69 of file archEnums.hpp.

◆ REG_SPEC [2/5]

#define REG_SPEC	(	_1,
		UPPER_NAME,
		_2,
		_3,
		_4,
		_5,
		_6 ) ID_REG_RV32_##UPPER_NAME,

Definition at line 69 of file archEnums.hpp.

◆ REG_SPEC [3/5]

#define REG_SPEC	(	UPPER_NAME,
		_1,
		_2,
		_3,
		_4,
		_5 ) ID_REG_AARCH64_##UPPER_NAME,

Definition at line 69 of file archEnums.hpp.

◆ REG_SPEC [4/5]

#define REG_SPEC	(	UPPER_NAME,
		_1,
		_2,
		_3,
		_4,
		_5 ) ID_REG_ARM32_##UPPER_NAME,

Definition at line 69 of file archEnums.hpp.