riscvSpecifications.cpp File Reference

#include <cassert>
#include <triton/architecture.hpp>
#include <triton/cpuSize.hpp>
#include <triton/exceptions.hpp>
#include <triton/externalLibs.hpp>
#include <triton/riscvSpecifications.hpp>
#include "triton/riscv64.spec"
#include "triton/riscv32.spec"

Go to the source code of this file.

Namespaces
namespace	triton
	The Triton namespace.
namespace	triton::arch
	The Architecture namespace.
namespace	triton::arch::riscv
	The riscv namespace.

Macros
#define	REG_SPEC(CS_UPPER_NAME, UPPER_NAME, LOWER_NAME, ABI_NAME, RISCV_UPPER, RISCV_LOWER, MUTABLE)
#define	REG_SPEC_NO_CAPSTONE   REG_SPEC
#define	REG_SPEC(CS_UPPER_NAME, UPPER_NAME, LOWER_NAME, ABI_NAME, RISCV_UPPER, RISCV_LOWER, MUTABLE)
#define	REG_SPEC_NO_CAPSTONE   REG_SPEC
#define	REG_SPEC(CS_UPPER_NAME, UPPER_NAME, _1, _2, _3, _4, _5)
#define	REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6, _7)
#define	REG_SPEC(CS_UPPER_NAME, UPPER_NAME, _1, _2, _3, _4, _5)
#define	REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6, _7)

Macro Definition Documentation

REG_SPEC [1/4]

#define REG_SPEC	(		CS_UPPER_NAME,
			UPPER_NAME,
			_1,
			_2,
			_3,
			_4,
			_5 )

Value:

          case triton::extlibs::capstone::RISCV_REG_##CS_UPPER_NAME:     \
            tritonId = triton::arch::ID_REG_RV64_##UPPER_NAME;           \
            break;

REG_SPEC [2/4]

#define REG_SPEC	(		CS_UPPER_NAME,
			UPPER_NAME,
			_1,
			_2,
			_3,
			_4,
			_5 )

Value:

          case triton::extlibs::capstone::RISCV_REG_##CS_UPPER_NAME:     \
            tritonId = triton::arch::ID_REG_RV32_##UPPER_NAME;           \
            break;

REG_SPEC [3/4]

#define REG_SPEC	(		CS_UPPER_NAME,
			UPPER_NAME,
			LOWER_NAME,
			ABI_NAME,
			RISCV_UPPER,
			RISCV_LOWER,
			MUTABLE )

Value:

            id2reg.emplace(ID_REG_RV64_##UPPER_NAME,                                                           \
                               triton::arch::Register(triton::arch::ID_REG_RV64_##UPPER_NAME,                  \
                                                      #LOWER_NAME,                                             \
                                                      triton::arch::ID_REG_RV64_##UPPER_NAME,                  \
                                                      RISCV_UPPER,                                             \
                                                      RISCV_LOWER,                                             \
                                                      MUTABLE)                                                 \
                              );                                                                               \
            name2id.emplace(#LOWER_NAME, ID_REG_RV64_##UPPER_NAME);                                            \
            name2id.emplace(#ABI_NAME,   ID_REG_RV64_##UPPER_NAME);

REG_SPEC [4/4]

#define REG_SPEC	(		CS_UPPER_NAME,
			UPPER_NAME,
			LOWER_NAME,
			ABI_NAME,
			RISCV_UPPER,
			RISCV_LOWER,
			MUTABLE )

Value:

            id2reg.emplace(ID_REG_RV32_##UPPER_NAME,                                                           \
                               triton::arch::Register(triton::arch::ID_REG_RV32_##UPPER_NAME,                  \
                                                      #LOWER_NAME,                                             \
                                                      triton::arch::ID_REG_RV32_##UPPER_NAME,                  \
                                                      RISCV_UPPER,                                             \
                                                      RISCV_LOWER,                                             \
                                                      MUTABLE)                                                 \
                              );                                                                               \
            name2id.emplace(#LOWER_NAME, ID_REG_RV32_##UPPER_NAME);                                            \
            name2id.emplace(#ABI_NAME,   ID_REG_RV32_##UPPER_NAME);