libTriton version 1.0 build 1592
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riscvSpecifications.cpp
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1
2/*
3** Copyright (C) - Triton
4**
5** This program is under the terms of the Apache License 2.0.
6*/
7
8#include <cassert>
9
10#include <triton/architecture.hpp>
11#include <triton/cpuSize.hpp>
12#include <triton/exceptions.hpp>
13#include <triton/externalLibs.hpp>
14#include <triton/riscvSpecifications.hpp>
15
16
17
18namespace triton {
19 namespace arch {
20 namespace riscv {
21
22 riscvSpecifications::riscvSpecifications(triton::arch::architecture_e arch) {
23 if (arch != triton::arch::ARCH_RV64 && arch != triton::arch::ARCH_RV32)
24 throw triton::exceptions::Architecture("riscvSpecifications::riscvSpecifications(): Invalid architecture.");
25
26 if (arch == triton::arch::ARCH_RV64) {
27 // Fill id2reg and name2id with those available in riscv from spec
28 #define REG_SPEC(CS_UPPER_NAME, UPPER_NAME, LOWER_NAME, ABI_NAME, RISCV_UPPER, RISCV_LOWER, MUTABLE) \
29 id2reg.emplace(ID_REG_RV64_##UPPER_NAME, \
30 triton::arch::Register(triton::arch::ID_REG_RV64_##UPPER_NAME, \
31 #LOWER_NAME, \
32 triton::arch::ID_REG_RV64_##UPPER_NAME, \
33 RISCV_UPPER, \
34 RISCV_LOWER, \
35 MUTABLE) \
36 ); \
37 name2id.emplace(#LOWER_NAME, ID_REG_RV64_##UPPER_NAME); \
38 name2id.emplace(#ABI_NAME, ID_REG_RV64_##UPPER_NAME);
39 // Handle register not available in capstone as normal registers
40 #define REG_SPEC_NO_CAPSTONE REG_SPEC
41 #include "triton/riscv64.spec"
42 }
43 else { // RV32
44 // Fill id2reg and name2id with those available in riscv32 from spec
45 #define REG_SPEC(CS_UPPER_NAME, UPPER_NAME, LOWER_NAME, ABI_NAME, RISCV_UPPER, RISCV_LOWER, MUTABLE) \
46 id2reg.emplace(ID_REG_RV32_##UPPER_NAME, \
47 triton::arch::Register(triton::arch::ID_REG_RV32_##UPPER_NAME, \
48 #LOWER_NAME, \
49 triton::arch::ID_REG_RV32_##UPPER_NAME, \
50 RISCV_UPPER, \
51 RISCV_LOWER, \
52 MUTABLE) \
53 ); \
54 name2id.emplace(#LOWER_NAME, ID_REG_RV32_##UPPER_NAME); \
55 name2id.emplace(#ABI_NAME, ID_REG_RV32_##UPPER_NAME);
56 // Handle register not available in capstone as normal registers
57 #define REG_SPEC_NO_CAPSTONE REG_SPEC
58 #include "triton/riscv32.spec"
59 }
60 }
61
62
63 triton::arch::register_e riscvSpecifications::capstoneRegisterToTritonRegister64(triton::uint32 id) const {
64 triton::arch::register_e tritonId = triton::arch::ID_REG_INVALID;
65 switch (id) {
66 // Convert registers from capstone value to triton value
67 #define REG_SPEC(CS_UPPER_NAME, UPPER_NAME, _1, _2, _3, _4, _5) \
68 case triton::extlibs::capstone::RISCV_REG_##CS_UPPER_NAME: \
69 tritonId = triton::arch::ID_REG_RV64_##UPPER_NAME; \
70 break;
71 // Ignore registers not available in capstone
72 #define REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6, _7)
73 #include "triton/riscv64.spec"
74
75 default:
76 tritonId = triton::arch::ID_REG_INVALID;
77 break;
78
79 }
80 return tritonId;
81 }
82
83
84 triton::arch::register_e riscvSpecifications::capstoneRegisterToTritonRegister32(triton::uint32 id) const {
85 triton::arch::register_e tritonId = triton::arch::ID_REG_INVALID;
86 switch (id) {
87 // Convert registers from capstone value to triton value
88 #define REG_SPEC(CS_UPPER_NAME, UPPER_NAME, _1, _2, _3, _4, _5) \
89 case triton::extlibs::capstone::RISCV_REG_##CS_UPPER_NAME: \
90 tritonId = triton::arch::ID_REG_RV32_##UPPER_NAME; \
91 break;
92 // Ignore registers not available in capstone
93 #define REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6, _7)
94 #include "triton/riscv32.spec"
95
96 default:
97 tritonId = triton::arch::ID_REG_INVALID;
98 break;
99
100 }
101 return tritonId;
102 }
103
104
105 triton::uint32 riscvSpecifications::capstoneInstructionToTritonInstruction(triton::uint32 id) const {
106 triton::uint32 tritonId = triton::arch::riscv::ID_INS_INVALID;
107
108 switch (id) {
109 case triton::extlibs::capstone::RISCV_INS_INVALID:
110 tritonId = triton::arch::riscv::ID_INS_INVALID;
111 break;
112
113 case triton::extlibs::capstone::RISCV_INS_ADD:
114 tritonId = triton::arch::riscv::ID_INS_ADD;
115 break;
116
117 case triton::extlibs::capstone::RISCV_INS_ADDI:
118 tritonId = triton::arch::riscv::ID_INS_ADDI;
119 break;
120
121 case triton::extlibs::capstone::RISCV_INS_ADDIW:
122 tritonId = triton::arch::riscv::ID_INS_ADDIW;
123 break;
124
125 case triton::extlibs::capstone::RISCV_INS_ADDW:
126 tritonId = triton::arch::riscv::ID_INS_ADDW;
127 break;
128
129 case triton::extlibs::capstone::RISCV_INS_AMOADD_D:
130 tritonId = triton::arch::riscv::ID_INS_AMOADD_D;
131 break;
132
133 case triton::extlibs::capstone::RISCV_INS_AMOADD_D_AQ:
134 tritonId = triton::arch::riscv::ID_INS_AMOADD_D_AQ;
135 break;
136
137 case triton::extlibs::capstone::RISCV_INS_AMOADD_D_AQ_RL:
138 tritonId = triton::arch::riscv::ID_INS_AMOADD_D_AQ_RL;
139 break;
140
141 case triton::extlibs::capstone::RISCV_INS_AMOADD_D_RL:
142 tritonId = triton::arch::riscv::ID_INS_AMOADD_D_RL;
143 break;
144
145 case triton::extlibs::capstone::RISCV_INS_AMOADD_W:
146 tritonId = triton::arch::riscv::ID_INS_AMOADD_W;
147 break;
148
149 case triton::extlibs::capstone::RISCV_INS_AMOADD_W_AQ:
150 tritonId = triton::arch::riscv::ID_INS_AMOADD_W_AQ;
151 break;
152
153 case triton::extlibs::capstone::RISCV_INS_AMOADD_W_AQ_RL:
154 tritonId = triton::arch::riscv::ID_INS_AMOADD_W_AQ_RL;
155 break;
156
157 case triton::extlibs::capstone::RISCV_INS_AMOADD_W_RL:
158 tritonId = triton::arch::riscv::ID_INS_AMOADD_W_RL;
159 break;
160
161 case triton::extlibs::capstone::RISCV_INS_AMOAND_D:
162 tritonId = triton::arch::riscv::ID_INS_AMOAND_D;
163 break;
164
165 case triton::extlibs::capstone::RISCV_INS_AMOAND_D_AQ:
166 tritonId = triton::arch::riscv::ID_INS_AMOAND_D_AQ;
167 break;
168
169 case triton::extlibs::capstone::RISCV_INS_AMOAND_D_AQ_RL:
170 tritonId = triton::arch::riscv::ID_INS_AMOAND_D_AQ_RL;
171 break;
172
173 case triton::extlibs::capstone::RISCV_INS_AMOAND_D_RL:
174 tritonId = triton::arch::riscv::ID_INS_AMOAND_D_RL;
175 break;
176
177 case triton::extlibs::capstone::RISCV_INS_AMOAND_W:
178 tritonId = triton::arch::riscv::ID_INS_AMOAND_W;
179 break;
180
181 case triton::extlibs::capstone::RISCV_INS_AMOAND_W_AQ:
182 tritonId = triton::arch::riscv::ID_INS_AMOAND_W_AQ;
183 break;
184
185 case triton::extlibs::capstone::RISCV_INS_AMOAND_W_AQ_RL:
186 tritonId = triton::arch::riscv::ID_INS_AMOAND_W_AQ_RL;
187 break;
188
189 case triton::extlibs::capstone::RISCV_INS_AMOAND_W_RL:
190 tritonId = triton::arch::riscv::ID_INS_AMOAND_W_RL;
191 break;
192
193 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_D:
194 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_D;
195 break;
196
197 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_D_AQ:
198 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_D_AQ;
199 break;
200
201 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_D_AQ_RL:
202 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_D_AQ_RL;
203 break;
204
205 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_D_RL:
206 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_D_RL;
207 break;
208
209 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_W:
210 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_W;
211 break;
212
213 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_W_AQ:
214 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_W_AQ;
215 break;
216
217 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_W_AQ_RL:
218 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_W_AQ_RL;
219 break;
220
221 case triton::extlibs::capstone::RISCV_INS_AMOMAXU_W_RL:
222 tritonId = triton::arch::riscv::ID_INS_AMOMAXU_W_RL;
223 break;
224
225 case triton::extlibs::capstone::RISCV_INS_AMOMAX_D:
226 tritonId = triton::arch::riscv::ID_INS_AMOMAX_D;
227 break;
228
229 case triton::extlibs::capstone::RISCV_INS_AMOMAX_D_AQ:
230 tritonId = triton::arch::riscv::ID_INS_AMOMAX_D_AQ;
231 break;
232
233 case triton::extlibs::capstone::RISCV_INS_AMOMAX_D_AQ_RL:
234 tritonId = triton::arch::riscv::ID_INS_AMOMAX_D_AQ_RL;
235 break;
236
237 case triton::extlibs::capstone::RISCV_INS_AMOMAX_D_RL:
238 tritonId = triton::arch::riscv::ID_INS_AMOMAX_D_RL;
239 break;
240
241 case triton::extlibs::capstone::RISCV_INS_AMOMAX_W:
242 tritonId = triton::arch::riscv::ID_INS_AMOMAX_W;
243 break;
244
245 case triton::extlibs::capstone::RISCV_INS_AMOMAX_W_AQ:
246 tritonId = triton::arch::riscv::ID_INS_AMOMAX_W_AQ;
247 break;
248
249 case triton::extlibs::capstone::RISCV_INS_AMOMAX_W_AQ_RL:
250 tritonId = triton::arch::riscv::ID_INS_AMOMAX_W_AQ_RL;
251 break;
252
253 case triton::extlibs::capstone::RISCV_INS_AMOMAX_W_RL:
254 tritonId = triton::arch::riscv::ID_INS_AMOMAX_W_RL;
255 break;
256
257 case triton::extlibs::capstone::RISCV_INS_AMOMINU_D:
258 tritonId = triton::arch::riscv::ID_INS_AMOMINU_D;
259 break;
260
261 case triton::extlibs::capstone::RISCV_INS_AMOMINU_D_AQ:
262 tritonId = triton::arch::riscv::ID_INS_AMOMINU_D_AQ;
263 break;
264
265 case triton::extlibs::capstone::RISCV_INS_AMOMINU_D_AQ_RL:
266 tritonId = triton::arch::riscv::ID_INS_AMOMINU_D_AQ_RL;
267 break;
268
269 case triton::extlibs::capstone::RISCV_INS_AMOMINU_D_RL:
270 tritonId = triton::arch::riscv::ID_INS_AMOMINU_D_RL;
271 break;
272
273 case triton::extlibs::capstone::RISCV_INS_AMOMINU_W:
274 tritonId = triton::arch::riscv::ID_INS_AMOMINU_W;
275 break;
276
277 case triton::extlibs::capstone::RISCV_INS_AMOMINU_W_AQ:
278 tritonId = triton::arch::riscv::ID_INS_AMOMINU_W_AQ;
279 break;
280
281 case triton::extlibs::capstone::RISCV_INS_AMOMINU_W_AQ_RL:
282 tritonId = triton::arch::riscv::ID_INS_AMOMINU_W_AQ_RL;
283 break;
284
285 case triton::extlibs::capstone::RISCV_INS_AMOMINU_W_RL:
286 tritonId = triton::arch::riscv::ID_INS_AMOMINU_W_RL;
287 break;
288
289 case triton::extlibs::capstone::RISCV_INS_AMOMIN_D:
290 tritonId = triton::arch::riscv::ID_INS_AMOMIN_D;
291 break;
292
293 case triton::extlibs::capstone::RISCV_INS_AMOMIN_D_AQ:
294 tritonId = triton::arch::riscv::ID_INS_AMOMIN_D_AQ;
295 break;
296
297 case triton::extlibs::capstone::RISCV_INS_AMOMIN_D_AQ_RL:
298 tritonId = triton::arch::riscv::ID_INS_AMOMIN_D_AQ_RL;
299 break;
300
301 case triton::extlibs::capstone::RISCV_INS_AMOMIN_D_RL:
302 tritonId = triton::arch::riscv::ID_INS_AMOMIN_D_RL;
303 break;
304
305 case triton::extlibs::capstone::RISCV_INS_AMOMIN_W:
306 tritonId = triton::arch::riscv::ID_INS_AMOMIN_W;
307 break;
308
309 case triton::extlibs::capstone::RISCV_INS_AMOMIN_W_AQ:
310 tritonId = triton::arch::riscv::ID_INS_AMOMIN_W_AQ;
311 break;
312
313 case triton::extlibs::capstone::RISCV_INS_AMOMIN_W_AQ_RL:
314 tritonId = triton::arch::riscv::ID_INS_AMOMIN_W_AQ_RL;
315 break;
316
317 case triton::extlibs::capstone::RISCV_INS_AMOMIN_W_RL:
318 tritonId = triton::arch::riscv::ID_INS_AMOMIN_W_RL;
319 break;
320
321 case triton::extlibs::capstone::RISCV_INS_AMOOR_D:
322 tritonId = triton::arch::riscv::ID_INS_AMOOR_D;
323 break;
324
325 case triton::extlibs::capstone::RISCV_INS_AMOOR_D_AQ:
326 tritonId = triton::arch::riscv::ID_INS_AMOOR_D_AQ;
327 break;
328
329 case triton::extlibs::capstone::RISCV_INS_AMOOR_D_AQ_RL:
330 tritonId = triton::arch::riscv::ID_INS_AMOOR_D_AQ_RL;
331 break;
332
333 case triton::extlibs::capstone::RISCV_INS_AMOOR_D_RL:
334 tritonId = triton::arch::riscv::ID_INS_AMOOR_D_RL;
335 break;
336
337 case triton::extlibs::capstone::RISCV_INS_AMOOR_W:
338 tritonId = triton::arch::riscv::ID_INS_AMOOR_W;
339 break;
340
341 case triton::extlibs::capstone::RISCV_INS_AMOOR_W_AQ:
342 tritonId = triton::arch::riscv::ID_INS_AMOOR_W_AQ;
343 break;
344
345 case triton::extlibs::capstone::RISCV_INS_AMOOR_W_AQ_RL:
346 tritonId = triton::arch::riscv::ID_INS_AMOOR_W_AQ_RL;
347 break;
348
349 case triton::extlibs::capstone::RISCV_INS_AMOOR_W_RL:
350 tritonId = triton::arch::riscv::ID_INS_AMOOR_W_RL;
351 break;
352
353 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_D:
354 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_D;
355 break;
356
357 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_D_AQ:
358 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_D_AQ;
359 break;
360
361 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_D_AQ_RL:
362 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_D_AQ_RL;
363 break;
364
365 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_D_RL:
366 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_D_RL;
367 break;
368
369 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_W:
370 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_W;
371 break;
372
373 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_W_AQ:
374 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_W_AQ;
375 break;
376
377 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_W_AQ_RL:
378 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_W_AQ_RL;
379 break;
380
381 case triton::extlibs::capstone::RISCV_INS_AMOSWAP_W_RL:
382 tritonId = triton::arch::riscv::ID_INS_AMOSWAP_W_RL;
383 break;
384
385 case triton::extlibs::capstone::RISCV_INS_AMOXOR_D:
386 tritonId = triton::arch::riscv::ID_INS_AMOXOR_D;
387 break;
388
389 case triton::extlibs::capstone::RISCV_INS_AMOXOR_D_AQ:
390 tritonId = triton::arch::riscv::ID_INS_AMOXOR_D_AQ;
391 break;
392
393 case triton::extlibs::capstone::RISCV_INS_AMOXOR_D_AQ_RL:
394 tritonId = triton::arch::riscv::ID_INS_AMOXOR_D_AQ_RL;
395 break;
396
397 case triton::extlibs::capstone::RISCV_INS_AMOXOR_D_RL:
398 tritonId = triton::arch::riscv::ID_INS_AMOXOR_D_RL;
399 break;
400
401 case triton::extlibs::capstone::RISCV_INS_AMOXOR_W:
402 tritonId = triton::arch::riscv::ID_INS_AMOXOR_W;
403 break;
404
405 case triton::extlibs::capstone::RISCV_INS_AMOXOR_W_AQ:
406 tritonId = triton::arch::riscv::ID_INS_AMOXOR_W_AQ;
407 break;
408
409 case triton::extlibs::capstone::RISCV_INS_AMOXOR_W_AQ_RL:
410 tritonId = triton::arch::riscv::ID_INS_AMOXOR_W_AQ_RL;
411 break;
412
413 case triton::extlibs::capstone::RISCV_INS_AMOXOR_W_RL:
414 tritonId = triton::arch::riscv::ID_INS_AMOXOR_W_RL;
415 break;
416
417 case triton::extlibs::capstone::RISCV_INS_AND:
418 tritonId = triton::arch::riscv::ID_INS_AND;
419 break;
420
421 case triton::extlibs::capstone::RISCV_INS_ANDI:
422 tritonId = triton::arch::riscv::ID_INS_ANDI;
423 break;
424
425 case triton::extlibs::capstone::RISCV_INS_AUIPC:
426 tritonId = triton::arch::riscv::ID_INS_AUIPC;
427 break;
428
429 case triton::extlibs::capstone::RISCV_INS_BEQ:
430 tritonId = triton::arch::riscv::ID_INS_BEQ;
431 break;
432
433 case triton::extlibs::capstone::RISCV_INS_BGE:
434 tritonId = triton::arch::riscv::ID_INS_BGE;
435 break;
436
437 case triton::extlibs::capstone::RISCV_INS_BGEU:
438 tritonId = triton::arch::riscv::ID_INS_BGEU;
439 break;
440
441 case triton::extlibs::capstone::RISCV_INS_BLT:
442 tritonId = triton::arch::riscv::ID_INS_BLT;
443 break;
444
445 case triton::extlibs::capstone::RISCV_INS_BLTU:
446 tritonId = triton::arch::riscv::ID_INS_BLTU;
447 break;
448
449 case triton::extlibs::capstone::RISCV_INS_BNE:
450 tritonId = triton::arch::riscv::ID_INS_BNE;
451 break;
452
453 case triton::extlibs::capstone::RISCV_INS_CSRRC:
454 tritonId = triton::arch::riscv::ID_INS_CSRRC;
455 break;
456
457 case triton::extlibs::capstone::RISCV_INS_CSRRCI:
458 tritonId = triton::arch::riscv::ID_INS_CSRRCI;
459 break;
460
461 case triton::extlibs::capstone::RISCV_INS_CSRRS:
462 tritonId = triton::arch::riscv::ID_INS_CSRRS;
463 break;
464
465 case triton::extlibs::capstone::RISCV_INS_CSRRSI:
466 tritonId = triton::arch::riscv::ID_INS_CSRRSI;
467 break;
468
469 case triton::extlibs::capstone::RISCV_INS_CSRRW:
470 tritonId = triton::arch::riscv::ID_INS_CSRRW;
471 break;
472
473 case triton::extlibs::capstone::RISCV_INS_CSRRWI:
474 tritonId = triton::arch::riscv::ID_INS_CSRRWI;
475 break;
476 /* Compressed instructions */
477 case triton::extlibs::capstone::RISCV_INS_C_ADD:
478 tritonId = triton::arch::riscv::ID_INS_C_ADD;
479 break;
480
481 case triton::extlibs::capstone::RISCV_INS_C_ADDI:
482 tritonId = triton::arch::riscv::ID_INS_C_ADDI;
483 break;
484
485 case triton::extlibs::capstone::RISCV_INS_C_ADDI16SP:
486 tritonId = triton::arch::riscv::ID_INS_C_ADDI16SP;
487 break;
488
489 case triton::extlibs::capstone::RISCV_INS_C_ADDI4SPN:
490 tritonId = triton::arch::riscv::ID_INS_C_ADDI4SPN;
491 break;
492
493 case triton::extlibs::capstone::RISCV_INS_C_ADDIW:
494 tritonId = triton::arch::riscv::ID_INS_C_ADDIW;
495 break;
496
497 case triton::extlibs::capstone::RISCV_INS_C_ADDW:
498 tritonId = triton::arch::riscv::ID_INS_C_ADDW;
499 break;
500
501 case triton::extlibs::capstone::RISCV_INS_C_AND:
502 tritonId = triton::arch::riscv::ID_INS_C_AND;
503 break;
504
505 case triton::extlibs::capstone::RISCV_INS_C_ANDI:
506 tritonId = triton::arch::riscv::ID_INS_C_ANDI;
507 break;
508
509 case triton::extlibs::capstone::RISCV_INS_C_BEQZ:
510 tritonId = triton::arch::riscv::ID_INS_C_BEQZ;
511 break;
512
513 case triton::extlibs::capstone::RISCV_INS_C_BNEZ:
514 tritonId = triton::arch::riscv::ID_INS_C_BNEZ;
515 break;
516
517 case triton::extlibs::capstone::RISCV_INS_C_EBREAK:
518 tritonId = triton::arch::riscv::ID_INS_C_EBREAK;
519 break;
520
521 case triton::extlibs::capstone::RISCV_INS_C_FLD:
522 tritonId = triton::arch::riscv::ID_INS_C_FLD;
523 break;
524
525 case triton::extlibs::capstone::RISCV_INS_C_FLDSP:
526 tritonId = triton::arch::riscv::ID_INS_C_FLDSP;
527 break;
528
529 case triton::extlibs::capstone::RISCV_INS_C_FLW:
530 tritonId = triton::arch::riscv::ID_INS_C_FLW;
531 break;
532
533 case triton::extlibs::capstone::RISCV_INS_C_FLWSP:
534 tritonId = triton::arch::riscv::ID_INS_C_FLWSP;
535 break;
536
537 case triton::extlibs::capstone::RISCV_INS_C_FSD:
538 tritonId = triton::arch::riscv::ID_INS_C_FSD;
539 break;
540
541 case triton::extlibs::capstone::RISCV_INS_C_FSDSP:
542 tritonId = triton::arch::riscv::ID_INS_C_FSDSP;
543 break;
544
545 case triton::extlibs::capstone::RISCV_INS_C_FSW:
546 tritonId = triton::arch::riscv::ID_INS_C_FSW;
547 break;
548
549 case triton::extlibs::capstone::RISCV_INS_C_FSWSP:
550 tritonId = triton::arch::riscv::ID_INS_C_FSWSP;
551 break;
552
553 case triton::extlibs::capstone::RISCV_INS_C_J:
554 tritonId = triton::arch::riscv::ID_INS_C_J;
555 break;
556
557 case triton::extlibs::capstone::RISCV_INS_C_JAL:
558 tritonId = triton::arch::riscv::ID_INS_C_JAL;
559 break;
560
561 case triton::extlibs::capstone::RISCV_INS_C_JALR:
562 tritonId = triton::arch::riscv::ID_INS_C_JALR;
563 break;
564
565 case triton::extlibs::capstone::RISCV_INS_C_JR:
566 tritonId = triton::arch::riscv::ID_INS_C_JR;
567 break;
568
569 case triton::extlibs::capstone::RISCV_INS_C_LD:
570 tritonId = triton::arch::riscv::ID_INS_C_LD;
571 break;
572
573 case triton::extlibs::capstone::RISCV_INS_C_LDSP:
574 tritonId = triton::arch::riscv::ID_INS_C_LDSP;
575 break;
576
577 case triton::extlibs::capstone::RISCV_INS_C_LI:
578 tritonId = triton::arch::riscv::ID_INS_C_LI;
579 break;
580
581 case triton::extlibs::capstone::RISCV_INS_C_LUI:
582 tritonId = triton::arch::riscv::ID_INS_C_LUI;
583 break;
584
585 case triton::extlibs::capstone::RISCV_INS_C_LW:
586 tritonId = triton::arch::riscv::ID_INS_C_LW;
587 break;
588
589 case triton::extlibs::capstone::RISCV_INS_C_LWSP:
590 tritonId = triton::arch::riscv::ID_INS_C_LWSP;
591 break;
592
593 case triton::extlibs::capstone::RISCV_INS_C_MV:
594 tritonId = triton::arch::riscv::ID_INS_C_MV;
595 break;
596
597 case triton::extlibs::capstone::RISCV_INS_C_NOP:
598 tritonId = triton::arch::riscv::ID_INS_C_NOP;
599 break;
600
601 case triton::extlibs::capstone::RISCV_INS_C_OR:
602 tritonId = triton::arch::riscv::ID_INS_C_OR;
603 break;
604
605 case triton::extlibs::capstone::RISCV_INS_C_SD:
606 tritonId = triton::arch::riscv::ID_INS_C_SD;
607 break;
608
609 case triton::extlibs::capstone::RISCV_INS_C_SDSP:
610 tritonId = triton::arch::riscv::ID_INS_C_SDSP;
611 break;
612
613 case triton::extlibs::capstone::RISCV_INS_C_SLLI:
614 tritonId = triton::arch::riscv::ID_INS_C_SLLI;
615 break;
616
617 case triton::extlibs::capstone::RISCV_INS_C_SRAI:
618 tritonId = triton::arch::riscv::ID_INS_C_SRAI;
619 break;
620
621 case triton::extlibs::capstone::RISCV_INS_C_SRLI:
622 tritonId = triton::arch::riscv::ID_INS_C_SRLI;
623 break;
624
625 case triton::extlibs::capstone::RISCV_INS_C_SUB:
626 tritonId = triton::arch::riscv::ID_INS_C_SUB;
627 break;
628
629 case triton::extlibs::capstone::RISCV_INS_C_SUBW:
630 tritonId = triton::arch::riscv::ID_INS_C_SUBW;
631 break;
632
633 case triton::extlibs::capstone::RISCV_INS_C_SW:
634 tritonId = triton::arch::riscv::ID_INS_C_SW;
635 break;
636
637 case triton::extlibs::capstone::RISCV_INS_C_SWSP:
638 tritonId = triton::arch::riscv::ID_INS_C_SWSP;
639 break;
640
641 case triton::extlibs::capstone::RISCV_INS_C_UNIMP:
642 tritonId = triton::arch::riscv::ID_INS_C_UNIMP;
643 break;
644
645 case triton::extlibs::capstone::RISCV_INS_C_XOR:
646 tritonId = triton::arch::riscv::ID_INS_C_XOR;
647 break;
648 /* End of compressed instructions */
649 case triton::extlibs::capstone::RISCV_INS_DIV:
650 tritonId = triton::arch::riscv::ID_INS_DIV;
651 break;
652
653 case triton::extlibs::capstone::RISCV_INS_DIVU:
654 tritonId = triton::arch::riscv::ID_INS_DIVU;
655 break;
656
657 case triton::extlibs::capstone::RISCV_INS_DIVUW:
658 tritonId = triton::arch::riscv::ID_INS_DIVUW;
659 break;
660
661 case triton::extlibs::capstone::RISCV_INS_DIVW:
662 tritonId = triton::arch::riscv::ID_INS_DIVW;
663 break;
664
665 case triton::extlibs::capstone::RISCV_INS_EBREAK:
666 tritonId = triton::arch::riscv::ID_INS_EBREAK;
667 break;
668
669 case triton::extlibs::capstone::RISCV_INS_ECALL:
670 tritonId = triton::arch::riscv::ID_INS_ECALL;
671 break;
672
673 case triton::extlibs::capstone::RISCV_INS_FADD_D:
674 tritonId = triton::arch::riscv::ID_INS_FADD_D;
675 break;
676
677 case triton::extlibs::capstone::RISCV_INS_FADD_S:
678 tritonId = triton::arch::riscv::ID_INS_FADD_S;
679 break;
680
681 case triton::extlibs::capstone::RISCV_INS_FCLASS_D:
682 tritonId = triton::arch::riscv::ID_INS_FCLASS_D;
683 break;
684
685 case triton::extlibs::capstone::RISCV_INS_FCLASS_S:
686 tritonId = triton::arch::riscv::ID_INS_FCLASS_S;
687 break;
688
689 case triton::extlibs::capstone::RISCV_INS_FCVT_D_L:
690 tritonId = triton::arch::riscv::ID_INS_FCVT_D_L;
691 break;
692
693 case triton::extlibs::capstone::RISCV_INS_FCVT_D_LU:
694 tritonId = triton::arch::riscv::ID_INS_FCVT_D_LU;
695 break;
696
697 case triton::extlibs::capstone::RISCV_INS_FCVT_D_S:
698 tritonId = triton::arch::riscv::ID_INS_FCVT_D_S;
699 break;
700
701 case triton::extlibs::capstone::RISCV_INS_FCVT_D_W:
702 tritonId = triton::arch::riscv::ID_INS_FCVT_D_W;
703 break;
704
705 case triton::extlibs::capstone::RISCV_INS_FCVT_D_WU:
706 tritonId = triton::arch::riscv::ID_INS_FCVT_D_WU;
707 break;
708
709 case triton::extlibs::capstone::RISCV_INS_FCVT_LU_D:
710 tritonId = triton::arch::riscv::ID_INS_FCVT_LU_D;
711 break;
712
713 case triton::extlibs::capstone::RISCV_INS_FCVT_LU_S:
714 tritonId = triton::arch::riscv::ID_INS_FCVT_LU_S;
715 break;
716
717 case triton::extlibs::capstone::RISCV_INS_FCVT_L_D:
718 tritonId = triton::arch::riscv::ID_INS_FCVT_L_D;
719 break;
720
721 case triton::extlibs::capstone::RISCV_INS_FCVT_L_S:
722 tritonId = triton::arch::riscv::ID_INS_FCVT_L_S;
723 break;
724
725 case triton::extlibs::capstone::RISCV_INS_FCVT_S_D:
726 tritonId = triton::arch::riscv::ID_INS_FCVT_S_D;
727 break;
728
729 case triton::extlibs::capstone::RISCV_INS_FCVT_S_L:
730 tritonId = triton::arch::riscv::ID_INS_FCVT_S_L;
731 break;
732
733 case triton::extlibs::capstone::RISCV_INS_FCVT_S_LU:
734 tritonId = triton::arch::riscv::ID_INS_FCVT_S_LU;
735 break;
736
737 case triton::extlibs::capstone::RISCV_INS_FCVT_S_W:
738 tritonId = triton::arch::riscv::ID_INS_FCVT_S_W;
739 break;
740
741 case triton::extlibs::capstone::RISCV_INS_FCVT_S_WU:
742 tritonId = triton::arch::riscv::ID_INS_FCVT_S_WU;
743 break;
744
745 case triton::extlibs::capstone::RISCV_INS_FCVT_WU_D:
746 tritonId = triton::arch::riscv::ID_INS_FCVT_WU_D;
747 break;
748
749 case triton::extlibs::capstone::RISCV_INS_FCVT_WU_S:
750 tritonId = triton::arch::riscv::ID_INS_FCVT_WU_S;
751 break;
752
753 case triton::extlibs::capstone::RISCV_INS_FCVT_W_D:
754 tritonId = triton::arch::riscv::ID_INS_FCVT_W_D;
755 break;
756
757 case triton::extlibs::capstone::RISCV_INS_FCVT_W_S:
758 tritonId = triton::arch::riscv::ID_INS_FCVT_W_S;
759 break;
760
761 case triton::extlibs::capstone::RISCV_INS_FDIV_D:
762 tritonId = triton::arch::riscv::ID_INS_FDIV_D;
763 break;
764
765 case triton::extlibs::capstone::RISCV_INS_FDIV_S:
766 tritonId = triton::arch::riscv::ID_INS_FDIV_S;
767 break;
768
769 case triton::extlibs::capstone::RISCV_INS_FENCE:
770 tritonId = triton::arch::riscv::ID_INS_FENCE;
771 break;
772
773 case triton::extlibs::capstone::RISCV_INS_FENCE_I:
774 tritonId = triton::arch::riscv::ID_INS_FENCE_I;
775 break;
776
777 case triton::extlibs::capstone::RISCV_INS_FENCE_TSO:
778 tritonId = triton::arch::riscv::ID_INS_FENCE_TSO;
779 break;
780
781 case triton::extlibs::capstone::RISCV_INS_FEQ_D:
782 tritonId = triton::arch::riscv::ID_INS_FEQ_D;
783 break;
784
785 case triton::extlibs::capstone::RISCV_INS_FEQ_S:
786 tritonId = triton::arch::riscv::ID_INS_FEQ_S;
787 break;
788
789 case triton::extlibs::capstone::RISCV_INS_FLD:
790 tritonId = triton::arch::riscv::ID_INS_FLD;
791 break;
792
793 case triton::extlibs::capstone::RISCV_INS_FLE_D:
794 tritonId = triton::arch::riscv::ID_INS_FLE_D;
795 break;
796
797 case triton::extlibs::capstone::RISCV_INS_FLE_S:
798 tritonId = triton::arch::riscv::ID_INS_FLE_S;
799 break;
800
801 case triton::extlibs::capstone::RISCV_INS_FLT_D:
802 tritonId = triton::arch::riscv::ID_INS_FLT_D;
803 break;
804
805 case triton::extlibs::capstone::RISCV_INS_FLT_S:
806 tritonId = triton::arch::riscv::ID_INS_FLT_S;
807 break;
808
809 case triton::extlibs::capstone::RISCV_INS_FLW:
810 tritonId = triton::arch::riscv::ID_INS_FLW;
811 break;
812
813 case triton::extlibs::capstone::RISCV_INS_FMADD_D:
814 tritonId = triton::arch::riscv::ID_INS_FMADD_D;
815 break;
816
817 case triton::extlibs::capstone::RISCV_INS_FMADD_S:
818 tritonId = triton::arch::riscv::ID_INS_FMADD_S;
819 break;
820
821 case triton::extlibs::capstone::RISCV_INS_FMAX_D:
822 tritonId = triton::arch::riscv::ID_INS_FMAX_D;
823 break;
824
825 case triton::extlibs::capstone::RISCV_INS_FMAX_S:
826 tritonId = triton::arch::riscv::ID_INS_FMAX_S;
827 break;
828
829 case triton::extlibs::capstone::RISCV_INS_FMIN_D:
830 tritonId = triton::arch::riscv::ID_INS_FMIN_D;
831 break;
832
833 case triton::extlibs::capstone::RISCV_INS_FMIN_S:
834 tritonId = triton::arch::riscv::ID_INS_FMIN_S;
835 break;
836
837 case triton::extlibs::capstone::RISCV_INS_FMSUB_D:
838 tritonId = triton::arch::riscv::ID_INS_FMSUB_D;
839 break;
840
841 case triton::extlibs::capstone::RISCV_INS_FMSUB_S:
842 tritonId = triton::arch::riscv::ID_INS_FMSUB_S;
843 break;
844
845 case triton::extlibs::capstone::RISCV_INS_FMUL_D:
846 tritonId = triton::arch::riscv::ID_INS_FMUL_D;
847 break;
848
849 case triton::extlibs::capstone::RISCV_INS_FMUL_S:
850 tritonId = triton::arch::riscv::ID_INS_FMUL_S;
851 break;
852
853 case triton::extlibs::capstone::RISCV_INS_FMV_D_X:
854 tritonId = triton::arch::riscv::ID_INS_FMV_D_X;
855 break;
856
857 case triton::extlibs::capstone::RISCV_INS_FMV_W_X:
858 tritonId = triton::arch::riscv::ID_INS_FMV_W_X;
859 break;
860
861 case triton::extlibs::capstone::RISCV_INS_FMV_X_D:
862 tritonId = triton::arch::riscv::ID_INS_FMV_X_D;
863 break;
864
865 case triton::extlibs::capstone::RISCV_INS_FMV_X_W:
866 tritonId = triton::arch::riscv::ID_INS_FMV_X_W;
867 break;
868
869 case triton::extlibs::capstone::RISCV_INS_FNMADD_D:
870 tritonId = triton::arch::riscv::ID_INS_FNMADD_D;
871 break;
872
873 case triton::extlibs::capstone::RISCV_INS_FNMADD_S:
874 tritonId = triton::arch::riscv::ID_INS_FNMADD_S;
875 break;
876
877 case triton::extlibs::capstone::RISCV_INS_FNMSUB_D:
878 tritonId = triton::arch::riscv::ID_INS_FNMSUB_D;
879 break;
880
881 case triton::extlibs::capstone::RISCV_INS_FNMSUB_S:
882 tritonId = triton::arch::riscv::ID_INS_FNMSUB_S;
883 break;
884
885 case triton::extlibs::capstone::RISCV_INS_FSD:
886 tritonId = triton::arch::riscv::ID_INS_FSD;
887 break;
888
889 case triton::extlibs::capstone::RISCV_INS_FSGNJN_D:
890 tritonId = triton::arch::riscv::ID_INS_FSGNJN_D;
891 break;
892
893 case triton::extlibs::capstone::RISCV_INS_FSGNJN_S:
894 tritonId = triton::arch::riscv::ID_INS_FSGNJN_S;
895 break;
896
897 case triton::extlibs::capstone::RISCV_INS_FSGNJX_D:
898 tritonId = triton::arch::riscv::ID_INS_FSGNJX_D;
899 break;
900
901 case triton::extlibs::capstone::RISCV_INS_FSGNJX_S:
902 tritonId = triton::arch::riscv::ID_INS_FSGNJX_S;
903 break;
904
905 case triton::extlibs::capstone::RISCV_INS_FSGNJ_D:
906 tritonId = triton::arch::riscv::ID_INS_FSGNJ_D;
907 break;
908
909 case triton::extlibs::capstone::RISCV_INS_FSGNJ_S:
910 tritonId = triton::arch::riscv::ID_INS_FSGNJ_S;
911 break;
912
913 case triton::extlibs::capstone::RISCV_INS_FSQRT_D:
914 tritonId = triton::arch::riscv::ID_INS_FSQRT_D;
915 break;
916
917 case triton::extlibs::capstone::RISCV_INS_FSQRT_S:
918 tritonId = triton::arch::riscv::ID_INS_FSQRT_S;
919 break;
920
921 case triton::extlibs::capstone::RISCV_INS_FSUB_D:
922 tritonId = triton::arch::riscv::ID_INS_FSUB_D;
923 break;
924
925 case triton::extlibs::capstone::RISCV_INS_FSUB_S:
926 tritonId = triton::arch::riscv::ID_INS_FSUB_S;
927 break;
928
929 case triton::extlibs::capstone::RISCV_INS_FSW:
930 tritonId = triton::arch::riscv::ID_INS_FSW;
931 break;
932
933 case triton::extlibs::capstone::RISCV_INS_JAL:
934 tritonId = triton::arch::riscv::ID_INS_JAL;
935 break;
936
937 case triton::extlibs::capstone::RISCV_INS_JALR:
938 tritonId = triton::arch::riscv::ID_INS_JALR;
939 break;
940
941 case triton::extlibs::capstone::RISCV_INS_LB:
942 tritonId = triton::arch::riscv::ID_INS_LB;
943 break;
944
945 case triton::extlibs::capstone::RISCV_INS_LBU:
946 tritonId = triton::arch::riscv::ID_INS_LBU;
947 break;
948
949 case triton::extlibs::capstone::RISCV_INS_LD:
950 tritonId = triton::arch::riscv::ID_INS_LD;
951 break;
952
953 case triton::extlibs::capstone::RISCV_INS_LH:
954 tritonId = triton::arch::riscv::ID_INS_LH;
955 break;
956
957 case triton::extlibs::capstone::RISCV_INS_LHU:
958 tritonId = triton::arch::riscv::ID_INS_LHU;
959 break;
960
961 case triton::extlibs::capstone::RISCV_INS_LR_D:
962 tritonId = triton::arch::riscv::ID_INS_LR_D;
963 break;
964
965 case triton::extlibs::capstone::RISCV_INS_LR_D_AQ:
966 tritonId = triton::arch::riscv::ID_INS_LR_D_AQ;
967 break;
968
969 case triton::extlibs::capstone::RISCV_INS_LR_D_AQ_RL:
970 tritonId = triton::arch::riscv::ID_INS_LR_D_AQ_RL;
971 break;
972
973 case triton::extlibs::capstone::RISCV_INS_LR_D_RL:
974 tritonId = triton::arch::riscv::ID_INS_LR_D_RL;
975 break;
976
977 case triton::extlibs::capstone::RISCV_INS_LR_W:
978 tritonId = triton::arch::riscv::ID_INS_LR_W;
979 break;
980
981 case triton::extlibs::capstone::RISCV_INS_LR_W_AQ:
982 tritonId = triton::arch::riscv::ID_INS_LR_W_AQ;
983 break;
984
985 case triton::extlibs::capstone::RISCV_INS_LR_W_AQ_RL:
986 tritonId = triton::arch::riscv::ID_INS_LR_W_AQ_RL;
987 break;
988
989 case triton::extlibs::capstone::RISCV_INS_LR_W_RL:
990 tritonId = triton::arch::riscv::ID_INS_LR_W_RL;
991 break;
992
993 case triton::extlibs::capstone::RISCV_INS_LUI:
994 tritonId = triton::arch::riscv::ID_INS_LUI;
995 break;
996
997 case triton::extlibs::capstone::RISCV_INS_LW:
998 tritonId = triton::arch::riscv::ID_INS_LW;
999 break;
1000
1001 case triton::extlibs::capstone::RISCV_INS_LWU:
1002 tritonId = triton::arch::riscv::ID_INS_LWU;
1003 break;
1004
1005 case triton::extlibs::capstone::RISCV_INS_MRET:
1006 tritonId = triton::arch::riscv::ID_INS_MRET;
1007 break;
1008
1009 case triton::extlibs::capstone::RISCV_INS_MUL:
1010 tritonId = triton::arch::riscv::ID_INS_MUL;
1011 break;
1012
1013 case triton::extlibs::capstone::RISCV_INS_MULH:
1014 tritonId = triton::arch::riscv::ID_INS_MULH;
1015 break;
1016
1017 case triton::extlibs::capstone::RISCV_INS_MULHSU:
1018 tritonId = triton::arch::riscv::ID_INS_MULHSU;
1019 break;
1020
1021 case triton::extlibs::capstone::RISCV_INS_MULHU:
1022 tritonId = triton::arch::riscv::ID_INS_MULHU;
1023 break;
1024
1025 case triton::extlibs::capstone::RISCV_INS_MULW:
1026 tritonId = triton::arch::riscv::ID_INS_MULW;
1027 break;
1028
1029 case triton::extlibs::capstone::RISCV_INS_OR:
1030 tritonId = triton::arch::riscv::ID_INS_OR;
1031 break;
1032
1033 case triton::extlibs::capstone::RISCV_INS_ORI:
1034 tritonId = triton::arch::riscv::ID_INS_ORI;
1035 break;
1036
1037 case triton::extlibs::capstone::RISCV_INS_REM:
1038 tritonId = triton::arch::riscv::ID_INS_REM;
1039 break;
1040
1041 case triton::extlibs::capstone::RISCV_INS_REMU:
1042 tritonId = triton::arch::riscv::ID_INS_REMU;
1043 break;
1044
1045 case triton::extlibs::capstone::RISCV_INS_REMUW:
1046 tritonId = triton::arch::riscv::ID_INS_REMUW;
1047 break;
1048
1049 case triton::extlibs::capstone::RISCV_INS_REMW:
1050 tritonId = triton::arch::riscv::ID_INS_REMW;
1051 break;
1052
1053 case triton::extlibs::capstone::RISCV_INS_SB:
1054 tritonId = triton::arch::riscv::ID_INS_SB;
1055 break;
1056
1057 case triton::extlibs::capstone::RISCV_INS_SC_D:
1058 tritonId = triton::arch::riscv::ID_INS_SC_D;
1059 break;
1060
1061 case triton::extlibs::capstone::RISCV_INS_SC_D_AQ:
1062 tritonId = triton::arch::riscv::ID_INS_SC_D_AQ;
1063 break;
1064
1065 case triton::extlibs::capstone::RISCV_INS_SC_D_AQ_RL:
1066 tritonId = triton::arch::riscv::ID_INS_SC_D_AQ_RL;
1067 break;
1068
1069 case triton::extlibs::capstone::RISCV_INS_SC_D_RL:
1070 tritonId = triton::arch::riscv::ID_INS_SC_D_RL;
1071 break;
1072
1073 case triton::extlibs::capstone::RISCV_INS_SC_W:
1074 tritonId = triton::arch::riscv::ID_INS_SC_W;
1075 break;
1076
1077 case triton::extlibs::capstone::RISCV_INS_SC_W_AQ:
1078 tritonId = triton::arch::riscv::ID_INS_SC_W_AQ;
1079 break;
1080
1081 case triton::extlibs::capstone::RISCV_INS_SC_W_AQ_RL:
1082 tritonId = triton::arch::riscv::ID_INS_SC_W_AQ_RL;
1083 break;
1084
1085 case triton::extlibs::capstone::RISCV_INS_SC_W_RL:
1086 tritonId = triton::arch::riscv::ID_INS_SC_W_RL;
1087 break;
1088
1089 case triton::extlibs::capstone::RISCV_INS_SD:
1090 tritonId = triton::arch::riscv::ID_INS_SD;
1091 break;
1092
1093 case triton::extlibs::capstone::RISCV_INS_SFENCE_VMA:
1094 tritonId = triton::arch::riscv::ID_INS_SFENCE_VMA;
1095 break;
1096
1097 case triton::extlibs::capstone::RISCV_INS_SH:
1098 tritonId = triton::arch::riscv::ID_INS_SH;
1099 break;
1100
1101 case triton::extlibs::capstone::RISCV_INS_SLL:
1102 tritonId = triton::arch::riscv::ID_INS_SLL;
1103 break;
1104
1105 case triton::extlibs::capstone::RISCV_INS_SLLI:
1106 tritonId = triton::arch::riscv::ID_INS_SLLI;
1107 break;
1108
1109 case triton::extlibs::capstone::RISCV_INS_SLLIW:
1110 tritonId = triton::arch::riscv::ID_INS_SLLIW;
1111 break;
1112
1113 case triton::extlibs::capstone::RISCV_INS_SLLW:
1114 tritonId = triton::arch::riscv::ID_INS_SLLW;
1115 break;
1116
1117 case triton::extlibs::capstone::RISCV_INS_SLT:
1118 tritonId = triton::arch::riscv::ID_INS_SLT;
1119 break;
1120
1121 case triton::extlibs::capstone::RISCV_INS_SLTI:
1122 tritonId = triton::arch::riscv::ID_INS_SLTI;
1123 break;
1124
1125 case triton::extlibs::capstone::RISCV_INS_SLTIU:
1126 tritonId = triton::arch::riscv::ID_INS_SLTIU;
1127 break;
1128
1129 case triton::extlibs::capstone::RISCV_INS_SLTU:
1130 tritonId = triton::arch::riscv::ID_INS_SLTU;
1131 break;
1132
1133 case triton::extlibs::capstone::RISCV_INS_SRA:
1134 tritonId = triton::arch::riscv::ID_INS_SRA;
1135 break;
1136
1137 case triton::extlibs::capstone::RISCV_INS_SRAI:
1138 tritonId = triton::arch::riscv::ID_INS_SRAI;
1139 break;
1140
1141 case triton::extlibs::capstone::RISCV_INS_SRAIW:
1142 tritonId = triton::arch::riscv::ID_INS_SRAIW;
1143 break;
1144
1145 case triton::extlibs::capstone::RISCV_INS_SRAW:
1146 tritonId = triton::arch::riscv::ID_INS_SRAW;
1147 break;
1148
1149 case triton::extlibs::capstone::RISCV_INS_SRET:
1150 tritonId = triton::arch::riscv::ID_INS_SRET;
1151 break;
1152
1153 case triton::extlibs::capstone::RISCV_INS_SRL:
1154 tritonId = triton::arch::riscv::ID_INS_SRL;
1155 break;
1156
1157 case triton::extlibs::capstone::RISCV_INS_SRLI:
1158 tritonId = triton::arch::riscv::ID_INS_SRLI;
1159 break;
1160
1161 case triton::extlibs::capstone::RISCV_INS_SRLIW:
1162 tritonId = triton::arch::riscv::ID_INS_SRLIW;
1163 break;
1164
1165 case triton::extlibs::capstone::RISCV_INS_SRLW:
1166 tritonId = triton::arch::riscv::ID_INS_SRLW;
1167 break;
1168
1169 case triton::extlibs::capstone::RISCV_INS_SUB:
1170 tritonId = triton::arch::riscv::ID_INS_SUB;
1171 break;
1172
1173 case triton::extlibs::capstone::RISCV_INS_SUBW:
1174 tritonId = triton::arch::riscv::ID_INS_SUBW;
1175 break;
1176
1177 case triton::extlibs::capstone::RISCV_INS_SW:
1178 tritonId = triton::arch::riscv::ID_INS_SW;
1179 break;
1180
1181 case triton::extlibs::capstone::RISCV_INS_UNIMP:
1182 tritonId = ID_INS_UNIMP;
1183 break;
1184
1185 case triton::extlibs::capstone::RISCV_INS_URET:
1186 tritonId = ID_INS_URET;
1187 break;
1188
1189 case triton::extlibs::capstone::RISCV_INS_WFI:
1190 tritonId = ID_INS_WFI;
1191 break;
1192
1193 case triton::extlibs::capstone::RISCV_INS_XOR:
1194 tritonId = ID_INS_XOR;
1195 break;
1196
1197 case triton::extlibs::capstone::RISCV_INS_XORI:
1198 tritonId = ID_INS_XORI;
1199 break;
1200 default:
1201 tritonId = triton::arch::riscv::ID_INS_INVALID;
1202 break;
1203 }
1204
1205 return tritonId;
1206 }
1207
1208
1209 triton::uint32 riscvSpecifications::getMemoryOperandSpecialSize(triton::uint32 id) const {
1210 switch (id) {
1211 case ID_INS_LB:
1212 case ID_INS_LBU:
1213 case ID_INS_SB:
1214 return 1;
1215 case ID_INS_LH:
1216 case ID_INS_LHU:
1217 case ID_INS_SH:
1218 return 2;
1219 case ID_INS_LW:
1220 case ID_INS_LWU:
1221 case ID_INS_SW:
1222 return 4;
1223 case ID_INS_LD:
1224 case ID_INS_SD:
1225 return 8;
1226 default:
1227 return 0;
1228 }
1229 }
1230
1231 }; /* riscv namespace */
1232 }; /* arch namespace */
1233}; /* triton namespace */
triton::arch::riscv::riscvSpecifications::capstoneInstructionToTritonInstruction
TRITON_EXPORT triton::uint32 capstoneInstructionToTritonInstruction(triton::uint32 id) const
Converts a capstone's instruction id to a triton's instruction id.
Definition riscvSpecifications.cpp:105
triton::arch::riscv::riscvSpecifications::getMemoryOperandSpecialSize
TRITON_EXPORT triton::uint32 getMemoryOperandSpecialSize(triton::uint32 id) const
Returns memory access size if it is specified by instruction.
Definition riscvSpecifications.cpp:1209
triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister32
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister32(triton::uint32 id) const
Converts a capstone's register id to a triton's register id for RV32.
Definition riscvSpecifications.cpp:84
triton::arch::riscv::riscvSpecifications::riscvSpecifications
TRITON_EXPORT riscvSpecifications(triton::arch::architecture_e)
Constructor.
Definition riscvSpecifications.cpp:22
triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister64
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister64(triton::uint32 id) const
Converts a capstone's register id to a triton's register id for RV64.
Definition riscvSpecifications.cpp:63
triton::exceptions::Architecture
The exception class used by architectures.
Definition exceptions.hpp:221
triton::arch::architecture_e
architecture_e
Definition archEnums.hpp:32
triton::arch::register_e
register_e
Types of register.
Definition archEnums.hpp:68
triton::arch::ID_REG_INVALID
@ ID_REG_INVALID
invalid = 0
Definition archEnums.hpp:69
triton::uint32
std::uint32_t uint32
unisgned 32-bits
Definition tritonTypes.hpp:39
triton
The Triton namespace.
Definition architecture.cpp:27
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