libTriton version 1.0 build 1592
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riscvSpecifications.hpp
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1//
3/*
4** Copyright (C) - Triton
5**
6** This program is under the terms of the Apache License 2.0.
7*/
8
9#ifndef TRITON_RISCVSPECIFICATIONS_H
10#define TRITON_RISCVSPECIFICATIONS_H
11
12#include <unordered_map>
13#include <string>
14
15#include <triton/archEnums.hpp>
16#include <triton/architecture.hpp>
17#include <triton/dllexport.hpp>
18#include <triton/register.hpp>
19
20
21
23namespace triton {
30 namespace arch {
38 namespace riscv {
46
47 class riscvSpecifications {
48 protected:
50 std::unordered_map<triton::arch::register_e, const triton::arch::Register> id2reg;
51 std::unordered_map<std::string, triton::arch::register_e> name2id;
52
53 public:
55 TRITON_EXPORT riscvSpecifications(triton::arch::architecture_e);
56
58 TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister64(triton::uint32 id) const;
59
61 TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister32(triton::uint32 id) const;
62
64 TRITON_EXPORT triton::uint32 capstoneInstructionToTritonInstruction(triton::uint32 id) const;
65
67 TRITON_EXPORT triton::arch::riscv::insn_group_e capstoneGroupToTritonGroup(triton::uint32 id) const;
68
70 TRITON_EXPORT triton::uint32 getMemoryOperandSpecialSize(triton::uint32 id) const;
71 };
72
74 const triton::arch::Instruction nop = triton::arch::Instruction("\x13\x00\x00\x00", 4);
75
77 enum instruction_e {
78 ID_INS_INVALID = 0,
79
80 ID_INS_ADD,
81 ID_INS_ADDI,
82 ID_INS_ADDIW,
83 ID_INS_ADDW,
84 ID_INS_AMOADD_D,
85 ID_INS_AMOADD_D_AQ,
86 ID_INS_AMOADD_D_AQ_RL,
87 ID_INS_AMOADD_D_RL,
88 ID_INS_AMOADD_W,
89 ID_INS_AMOADD_W_AQ,
90 ID_INS_AMOADD_W_AQ_RL,
91 ID_INS_AMOADD_W_RL,
92 ID_INS_AMOAND_D,
93 ID_INS_AMOAND_D_AQ,
94 ID_INS_AMOAND_D_AQ_RL,
95 ID_INS_AMOAND_D_RL,
96 ID_INS_AMOAND_W,
97 ID_INS_AMOAND_W_AQ,
98 ID_INS_AMOAND_W_AQ_RL,
99 ID_INS_AMOAND_W_RL,
100 ID_INS_AMOMAXU_D,
101 ID_INS_AMOMAXU_D_AQ,
102 ID_INS_AMOMAXU_D_AQ_RL,
103 ID_INS_AMOMAXU_D_RL,
104 ID_INS_AMOMAXU_W,
105 ID_INS_AMOMAXU_W_AQ,
106 ID_INS_AMOMAXU_W_AQ_RL,
107 ID_INS_AMOMAXU_W_RL,
108 ID_INS_AMOMAX_D,
109 ID_INS_AMOMAX_D_AQ,
110 ID_INS_AMOMAX_D_AQ_RL,
111 ID_INS_AMOMAX_D_RL,
112 ID_INS_AMOMAX_W,
113 ID_INS_AMOMAX_W_AQ,
114 ID_INS_AMOMAX_W_AQ_RL,
115 ID_INS_AMOMAX_W_RL,
116 ID_INS_AMOMINU_D,
117 ID_INS_AMOMINU_D_AQ,
118 ID_INS_AMOMINU_D_AQ_RL,
119 ID_INS_AMOMINU_D_RL,
120 ID_INS_AMOMINU_W,
121 ID_INS_AMOMINU_W_AQ,
122 ID_INS_AMOMINU_W_AQ_RL,
123 ID_INS_AMOMINU_W_RL,
124 ID_INS_AMOMIN_D,
125 ID_INS_AMOMIN_D_AQ,
126 ID_INS_AMOMIN_D_AQ_RL,
127 ID_INS_AMOMIN_D_RL,
128 ID_INS_AMOMIN_W,
129 ID_INS_AMOMIN_W_AQ,
130 ID_INS_AMOMIN_W_AQ_RL,
131 ID_INS_AMOMIN_W_RL,
132 ID_INS_AMOOR_D,
133 ID_INS_AMOOR_D_AQ,
134 ID_INS_AMOOR_D_AQ_RL,
135 ID_INS_AMOOR_D_RL,
136 ID_INS_AMOOR_W,
137 ID_INS_AMOOR_W_AQ,
138 ID_INS_AMOOR_W_AQ_RL,
139 ID_INS_AMOOR_W_RL,
140 ID_INS_AMOSWAP_D,
141 ID_INS_AMOSWAP_D_AQ,
142 ID_INS_AMOSWAP_D_AQ_RL,
143 ID_INS_AMOSWAP_D_RL,
144 ID_INS_AMOSWAP_W,
145 ID_INS_AMOSWAP_W_AQ,
146 ID_INS_AMOSWAP_W_AQ_RL,
147 ID_INS_AMOSWAP_W_RL,
148 ID_INS_AMOXOR_D,
149 ID_INS_AMOXOR_D_AQ,
150 ID_INS_AMOXOR_D_AQ_RL,
151 ID_INS_AMOXOR_D_RL,
152 ID_INS_AMOXOR_W,
153 ID_INS_AMOXOR_W_AQ,
154 ID_INS_AMOXOR_W_AQ_RL,
155 ID_INS_AMOXOR_W_RL,
156 ID_INS_AND,
157 ID_INS_ANDI,
158 ID_INS_AUIPC,
159 ID_INS_BEQ,
160 ID_INS_BGE,
161 ID_INS_BGEU,
162 ID_INS_BLT,
163 ID_INS_BLTU,
164 ID_INS_BNE,
165 ID_INS_CSRRC,
166 ID_INS_CSRRCI,
167 ID_INS_CSRRS,
168 ID_INS_CSRRSI,
169 ID_INS_CSRRW,
170 ID_INS_CSRRWI,
171 /* Compressed instructions */
172 ID_INS_C_ADD,
173 ID_INS_C_ADDI,
174 ID_INS_C_ADDI16SP,
175 ID_INS_C_ADDI4SPN,
176 ID_INS_C_ADDIW,
177 ID_INS_C_ADDW,
178 ID_INS_C_AND,
179 ID_INS_C_ANDI,
180 ID_INS_C_BEQZ,
181 ID_INS_C_BNEZ,
182 ID_INS_C_EBREAK,
183 ID_INS_C_FLD,
184 ID_INS_C_FLDSP,
185 ID_INS_C_FLW,
186 ID_INS_C_FLWSP,
187 ID_INS_C_FSD,
188 ID_INS_C_FSDSP,
189 ID_INS_C_FSW,
190 ID_INS_C_FSWSP,
191 ID_INS_C_J,
192 ID_INS_C_JAL,
193 ID_INS_C_JALR,
194 ID_INS_C_JR,
195 ID_INS_C_LD,
196 ID_INS_C_LDSP,
197 ID_INS_C_LI,
198 ID_INS_C_LUI,
199 ID_INS_C_LW,
200 ID_INS_C_LWSP,
201 ID_INS_C_MV,
202 ID_INS_C_NOP,
203 ID_INS_C_OR,
204 ID_INS_C_SD,
205 ID_INS_C_SDSP,
206 ID_INS_C_SLLI,
207 ID_INS_C_SRAI,
208 ID_INS_C_SRLI,
209 ID_INS_C_SUB,
210 ID_INS_C_SUBW,
211 ID_INS_C_SW,
212 ID_INS_C_SWSP,
213 ID_INS_C_UNIMP,
214 ID_INS_C_XOR,
215 /* End of compressed instructions */
216 ID_INS_DIV,
217 ID_INS_DIVU,
218 ID_INS_DIVUW,
219 ID_INS_DIVW,
220 ID_INS_EBREAK,
221 ID_INS_ECALL,
222 ID_INS_FADD_D,
223 ID_INS_FADD_S,
224 ID_INS_FCLASS_D,
225 ID_INS_FCLASS_S,
226 ID_INS_FCVT_D_L,
227 ID_INS_FCVT_D_LU,
228 ID_INS_FCVT_D_S,
229 ID_INS_FCVT_D_W,
230 ID_INS_FCVT_D_WU,
231 ID_INS_FCVT_LU_D,
232 ID_INS_FCVT_LU_S,
233 ID_INS_FCVT_L_D,
234 ID_INS_FCVT_L_S,
235 ID_INS_FCVT_S_D,
236 ID_INS_FCVT_S_L,
237 ID_INS_FCVT_S_LU,
238 ID_INS_FCVT_S_W,
239 ID_INS_FCVT_S_WU,
240 ID_INS_FCVT_WU_D,
241 ID_INS_FCVT_WU_S,
242 ID_INS_FCVT_W_D,
243 ID_INS_FCVT_W_S,
244 ID_INS_FDIV_D,
245 ID_INS_FDIV_S,
246 ID_INS_FENCE,
247 ID_INS_FENCE_I,
248 ID_INS_FENCE_TSO,
249 ID_INS_FEQ_D,
250 ID_INS_FEQ_S,
251 ID_INS_FLD,
252 ID_INS_FLE_D,
253 ID_INS_FLE_S,
254 ID_INS_FLT_D,
255 ID_INS_FLT_S,
256 ID_INS_FLW,
257 ID_INS_FMADD_D,
258 ID_INS_FMADD_S,
259 ID_INS_FMAX_D,
260 ID_INS_FMAX_S,
261 ID_INS_FMIN_D,
262 ID_INS_FMIN_S,
263 ID_INS_FMSUB_D,
264 ID_INS_FMSUB_S,
265 ID_INS_FMUL_D,
266 ID_INS_FMUL_S,
267 ID_INS_FMV_D_X,
268 ID_INS_FMV_W_X,
269 ID_INS_FMV_X_D,
270 ID_INS_FMV_X_W,
271 ID_INS_FNMADD_D,
272 ID_INS_FNMADD_S,
273 ID_INS_FNMSUB_D,
274 ID_INS_FNMSUB_S,
275 ID_INS_FSD,
276 ID_INS_FSGNJN_D,
277 ID_INS_FSGNJN_S,
278 ID_INS_FSGNJX_D,
279 ID_INS_FSGNJX_S,
280 ID_INS_FSGNJ_D,
281 ID_INS_FSGNJ_S,
282 ID_INS_FSQRT_D,
283 ID_INS_FSQRT_S,
284 ID_INS_FSUB_D,
285 ID_INS_FSUB_S,
286 ID_INS_FSW,
287 ID_INS_JAL,
288 ID_INS_JALR,
289 ID_INS_LB,
290 ID_INS_LBU,
291 ID_INS_LD,
292 ID_INS_LH,
293 ID_INS_LHU,
294 ID_INS_LR_D,
295 ID_INS_LR_D_AQ,
296 ID_INS_LR_D_AQ_RL,
297 ID_INS_LR_D_RL,
298 ID_INS_LR_W,
299 ID_INS_LR_W_AQ,
300 ID_INS_LR_W_AQ_RL,
301 ID_INS_LR_W_RL,
302 ID_INS_LUI,
303 ID_INS_LW,
304 ID_INS_LWU,
305 ID_INS_MRET,
306 ID_INS_MUL,
307 ID_INS_MULH,
308 ID_INS_MULHSU,
309 ID_INS_MULHU,
310 ID_INS_MULW,
311 ID_INS_OR,
312 ID_INS_ORI,
313 ID_INS_REM,
314 ID_INS_REMU,
315 ID_INS_REMUW,
316 ID_INS_REMW,
317 ID_INS_SB,
318 ID_INS_SC_D,
319 ID_INS_SC_D_AQ,
320 ID_INS_SC_D_AQ_RL,
321 ID_INS_SC_D_RL,
322 ID_INS_SC_W,
323 ID_INS_SC_W_AQ,
324 ID_INS_SC_W_AQ_RL,
325 ID_INS_SC_W_RL,
326 ID_INS_SD,
327 ID_INS_SFENCE_VMA,
328 ID_INS_SH,
329 ID_INS_SLL,
330 ID_INS_SLLI,
331 ID_INS_SLLIW,
332 ID_INS_SLLW,
333 ID_INS_SLT,
334 ID_INS_SLTI,
335 ID_INS_SLTIU,
336 ID_INS_SLTU,
337 ID_INS_SRA,
338 ID_INS_SRAI,
339 ID_INS_SRAIW,
340 ID_INS_SRAW,
341 ID_INS_SRET,
342 ID_INS_SRL,
343 ID_INS_SRLI,
344 ID_INS_SRLIW,
345 ID_INS_SRLW,
346 ID_INS_SUB,
347 ID_INS_SUBW,
348 ID_INS_SW,
349 ID_INS_UNIMP,
350 ID_INS_URET,
351 ID_INS_WFI,
352 ID_INS_XOR,
353 ID_INS_XORI,
354
355 ID_INS_ENDING,
356 };
357
359 };
361 };
363};
364
365#endif /* TRITON_RISCVSPECIFICATIONS_H */
triton::arch::Instruction
This class is used to represent an instruction.
Definition instruction.hpp:48
triton::arch::riscv::riscvSpecifications
The riscvSpecifications class defines specifications about the RV32 and RV64 CPU.
Definition riscvSpecifications.hpp:47
triton::arch::riscv::riscvSpecifications::capstoneGroupToTritonGroup
TRITON_EXPORT triton::arch::riscv::insn_group_e capstoneGroupToTritonGroup(triton::uint32 id) const
Converts a capstone's group id to a triton's group id.
triton::arch::riscv::riscvSpecifications::capstoneInstructionToTritonInstruction
TRITON_EXPORT triton::uint32 capstoneInstructionToTritonInstruction(triton::uint32 id) const
Converts a capstone's instruction id to a triton's instruction id.
Definition riscvSpecifications.cpp:105
triton::arch::riscv::riscvSpecifications::id2reg
std::unordered_map< triton::arch::register_e, const triton::arch::Register > id2reg
List of registers specification available for this architecture.
Definition riscvSpecifications.hpp:50
triton::arch::riscv::riscvSpecifications::getMemoryOperandSpecialSize
TRITON_EXPORT triton::uint32 getMemoryOperandSpecialSize(triton::uint32 id) const
Returns memory access size if it is specified by instruction.
Definition riscvSpecifications.cpp:1209
triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister32
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister32(triton::uint32 id) const
Converts a capstone's register id to a triton's register id for RV32.
Definition riscvSpecifications.cpp:84
triton::arch::riscv::riscvSpecifications::riscvSpecifications
TRITON_EXPORT riscvSpecifications(triton::arch::architecture_e)
Constructor.
Definition riscvSpecifications.cpp:22
triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister64
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister64(triton::uint32 id) const
Converts a capstone's register id to a triton's register id for RV64.
Definition riscvSpecifications.cpp:63
triton::arch::architecture_e
architecture_e
Definition archEnums.hpp:32
triton::arch::register_e
register_e
Types of register.
Definition archEnums.hpp:68
triton::arch::riscv::instruction_e
instruction_e
The list of opcodes.
Definition riscvSpecifications.hpp:77
triton::arch::riscv::nop
const triton::arch::Instruction nop
RISCV NOP instruction – ADDI x0, x0, 0.
Definition riscvSpecifications.hpp:74
triton::uint32
std::uint32_t uint32
unisgned 32-bits
Definition tritonTypes.hpp:39
triton
The Triton namespace.
Definition architecture.cpp:27
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