libTriton version 1.0 build 1592
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This class is used to describe the RV32 spec. More...
#include <riscv32Cpu.hpp>
Public Member Functions | |
TRITON_EXPORT | riscv32Cpu (triton::callbacks::Callbacks *callbacks=nullptr) |
Constructor. | |
TRITON_EXPORT | riscv32Cpu (const riscv32Cpu &other) |
Constructor. | |
virtual TRITON_EXPORT | ~riscv32Cpu () |
Destructor. | |
TRITON_EXPORT riscv32Cpu & | operator= (const riscv32Cpu &other) |
Copies a riscv32Cpu class. | |
TRITON_EXPORT bool | isGPR (triton::arch::register_e regId) const |
Returns true if regId is a GRP. | |
TRITON_EXPORT bool | isFPU (triton::arch::register_e regId) const |
Returns true if regId is a FPU register. | |
TRITON_EXPORT bool | isFlag (triton::arch::register_e regId) const |
Returns true if the register ID is a flag. | |
TRITON_EXPORT bool | isRegister (triton::arch::register_e regId) const |
Returns true if the register ID is a register. | |
TRITON_EXPORT bool | isRegisterValid (triton::arch::register_e regId) const |
Returns true if the register ID is valid. | |
TRITON_EXPORT bool | isThumb (void) const |
Returns true if the execution mode is Thumb. Only useful for Arm32. | |
TRITON_EXPORT bool | isMemoryExclusive (const triton::arch::MemoryAccess &mem) const |
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64. | |
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & | getAllRegisters (void) const |
Returns all registers. | |
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & | getConcreteMemory (void) const |
Return all memory. | |
TRITON_EXPORT const triton::arch::Register & | getParentRegister (const triton::arch::Register ®) const |
Returns parent register from a given one. | |
TRITON_EXPORT const triton::arch::Register & | getParentRegister (triton::arch::register_e id) const |
Returns parent register from a given one. | |
TRITON_EXPORT const triton::arch::Register & | getProgramCounter (void) const |
Returns the program counter register. | |
TRITON_EXPORT const triton::arch::Register & | getRegister (triton::arch::register_e id) const |
Returns register from id. | |
TRITON_EXPORT const triton::arch::Register & | getRegister (const std::string &name) const |
Returns register from name. | |
TRITON_EXPORT const triton::arch::Register & | getStackPointer (void) const |
Returns the stack pointer register. | |
TRITON_EXPORT std::set< const triton::arch::Register * > | getParentRegisters (void) const |
Returns all parent registers. | |
TRITON_EXPORT std::vector< triton::uint8 > | getConcreteMemoryAreaValue (triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const |
Returns the concrete value of a memory area. | |
TRITON_EXPORT triton::arch::endianness_e | getEndianness (void) const |
Returns the kind of endianness as triton::arch::endianness_e. | |
TRITON_EXPORT triton::uint32 | numberOfRegisters (void) const |
Returns the number of registers according to the CPU architecture. | |
TRITON_EXPORT triton::uint32 | gprBitSize (void) const |
Returns the bit in bit of the General Purpose Registers. | |
TRITON_EXPORT triton::uint32 | gprSize (void) const |
Returns the bit in byte of the General Purpose Registers. | |
TRITON_EXPORT triton::uint512 | getConcreteMemoryValue (const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const |
Returns the concrete value of memory cells. | |
TRITON_EXPORT triton::uint512 | getConcreteRegisterValue (const triton::arch::Register ®, bool execCallbacks=true) const |
Returns the concrete value of a register. | |
TRITON_EXPORT triton::uint8 | getConcreteMemoryValue (triton::uint64 addr, bool execCallbacks=true) const |
Returns the concrete value of a memory cell. | |
TRITON_EXPORT void | clear (void) |
Clears the architecture states (registers and memory). | |
TRITON_EXPORT void | disassembly (triton::arch::Instruction &inst) |
Disassembles the instruction according to the architecture. | |
TRITON_EXPORT void | setConcreteMemoryAreaValue (triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory area. | |
TRITON_EXPORT void | setConcreteMemoryAreaValue (triton::uint64 baseAddr, const void *area, triton::usize size, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory area. | |
TRITON_EXPORT void | setConcreteMemoryValue (const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of memory cells. | |
TRITON_EXPORT void | setConcreteMemoryValue (triton::uint64 addr, triton::uint8 value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory cell. | |
TRITON_EXPORT void | setConcreteRegisterValue (const triton::arch::Register ®, const triton::uint512 &value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a register. | |
TRITON_EXPORT void | setThumb (bool state) |
Sets CPU state to Thumb mode. | |
TRITON_EXPORT void | setMemoryExclusiveTag (const triton::arch::MemoryAccess &mem, bool tag) |
Sets exclusive memory access tag. Only valid for Arm32 and AArch64. | |
TRITON_EXPORT bool | isConcreteMemoryValueDefined (const triton::arch::MemoryAccess &mem) const |
Returns true if memory cells have a defined concrete value. | |
TRITON_EXPORT bool | isConcreteMemoryValueDefined (triton::uint64 baseAddr, triton::usize size=1) const |
Returns true if memory cells have a defined concrete value. | |
TRITON_EXPORT void | clearConcreteMemoryValue (const triton::arch::MemoryAccess &mem) |
Clears concrete values assigned to the memory cells. | |
TRITON_EXPORT void | clearConcreteMemoryValue (triton::uint64 baseAddr, triton::usize size=1) |
Clears concrete values assigned to the memory cells. | |
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virtual TRITON_EXPORT | ~CpuInterface () |
Destructor. | |
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TRITON_EXPORT | riscvSpecifications (triton::arch::architecture_e) |
Constructor. | |
TRITON_EXPORT triton::arch::register_e | capstoneRegisterToTritonRegister64 (triton::uint32 id) const |
Converts a capstone's register id to a triton's register id for RV64. | |
TRITON_EXPORT triton::arch::register_e | capstoneRegisterToTritonRegister32 (triton::uint32 id) const |
Converts a capstone's register id to a triton's register id for RV32. | |
TRITON_EXPORT triton::uint32 | capstoneInstructionToTritonInstruction (triton::uint32 id) const |
Converts a capstone's instruction id to a triton's instruction id. | |
TRITON_EXPORT triton::arch::riscv::insn_group_e | capstoneGroupToTritonGroup (triton::uint32 id) const |
Converts a capstone's group id to a triton's group id. | |
TRITON_EXPORT triton::uint32 | getMemoryOperandSpecialSize (triton::uint32 id) const |
Returns memory access size if it is specified by instruction. | |
This class is used to describe the RV32 spec.
Definition at line 53 of file riscv32Cpu.hpp.
triton::arch::riscv::riscv32Cpu::riscv32Cpu | ( | triton::callbacks::Callbacks * | callbacks = nullptr | ) |
Constructor.
Definition at line 26 of file riscv32Cpu.cpp.
triton::arch::riscv::riscv32Cpu::riscv32Cpu | ( | const riscv32Cpu & | other | ) |
Constructor.
Definition at line 35 of file riscv32Cpu.cpp.
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Destructor.
Definition at line 40 of file riscv32Cpu.cpp.
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Clears the architecture states (registers and memory).
Implements triton::arch::CpuInterface.
Definition at line 133 of file riscv32Cpu.cpp.
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Clears concrete values assigned to the memory cells.
Implements triton::arch::CpuInterface.
Definition at line 726 of file riscv32Cpu.cpp.
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Clears concrete values assigned to the memory cells.
Implements triton::arch::CpuInterface.
Definition at line 731 of file riscv32Cpu.cpp.
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Disassembles the instruction according to the architecture.
Implements triton::arch::CpuInterface.
Definition at line 324 of file riscv32Cpu.cpp.
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Returns all registers.
Implements triton::arch::CpuInterface.
Definition at line 257 of file riscv32Cpu.cpp.
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Return all memory.
Implements triton::arch::CpuInterface.
Definition at line 261 of file riscv32Cpu.cpp.
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Returns the concrete value of a memory area.
Implements triton::arch::CpuInterface.
Definition at line 471 of file riscv32Cpu.cpp.
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Returns the concrete value of memory cells.
Implements triton::arch::CpuInterface.
Definition at line 450 of file riscv32Cpu.cpp.
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Returns the concrete value of a memory cell.
Implements triton::arch::CpuInterface.
Definition at line 437 of file riscv32Cpu.cpp.
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Returns the concrete value of a register.
Implements triton::arch::CpuInterface.
Definition at line 481 of file riscv32Cpu.cpp.
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Returns the kind of endianness as triton::arch::endianness_e.
Implements triton::arch::CpuInterface.
Definition at line 212 of file riscv32Cpu.cpp.
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Returns parent register from a given one.
Implements triton::arch::CpuInterface.
Definition at line 305 of file riscv32Cpu.cpp.
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Returns parent register from a given one.
Implements triton::arch::CpuInterface.
Definition at line 310 of file riscv32Cpu.cpp.
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Returns all parent registers.
Implements triton::arch::CpuInterface.
Definition at line 265 of file riscv32Cpu.cpp.
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Returns the program counter register.
Implements triton::arch::CpuInterface.
Definition at line 315 of file riscv32Cpu.cpp.
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Returns register from name.
Implements triton::arch::CpuInterface.
Definition at line 294 of file riscv32Cpu.cpp.
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Returns register from id.
Implements triton::arch::CpuInterface.
Definition at line 285 of file riscv32Cpu.cpp.
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Returns the stack pointer register.
Implements triton::arch::CpuInterface.
Definition at line 320 of file riscv32Cpu.cpp.
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Returns the bit in bit of the General Purpose Registers.
Implements triton::arch::CpuInterface.
Definition at line 252 of file riscv32Cpu.cpp.
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Returns the bit in byte of the General Purpose Registers.
Implements triton::arch::CpuInterface.
Definition at line 247 of file riscv32Cpu.cpp.
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Returns true if memory cells have a defined concrete value.
Implements triton::arch::CpuInterface.
Definition at line 711 of file riscv32Cpu.cpp.
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Returns true if memory cells have a defined concrete value.
Implements triton::arch::CpuInterface.
Definition at line 716 of file riscv32Cpu.cpp.
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Returns true if the register ID is a flag.
Implements triton::arch::CpuInterface.
Definition at line 237 of file riscv32Cpu.cpp.
bool triton::arch::riscv::riscv32Cpu::isFPU | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a FPU register.
Definition at line 232 of file riscv32Cpu.cpp.
bool triton::arch::riscv::riscv32Cpu::isGPR | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a GRP.
Definition at line 227 of file riscv32Cpu.cpp.
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Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
Implements triton::arch::CpuInterface.
Definition at line 700 of file riscv32Cpu.cpp.
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Returns true if the register ID is a register.
Implements triton::arch::CpuInterface.
Definition at line 217 of file riscv32Cpu.cpp.
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Returns true if the register ID is valid.
Implements triton::arch::CpuInterface.
Definition at line 222 of file riscv32Cpu.cpp.
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Returns true if the execution mode is Thumb. Only useful for Arm32.
Implements triton::arch::CpuInterface.
Definition at line 689 of file riscv32Cpu.cpp.
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Returns the number of registers according to the CPU architecture.
Implements triton::arch::CpuInterface.
Definition at line 242 of file riscv32Cpu.cpp.
riscv32Cpu & triton::arch::riscv::riscv32Cpu::operator= | ( | const riscv32Cpu & | other | ) |
Copies a riscv32Cpu class.
Definition at line 206 of file riscv32Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory area.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 589 of file riscv32Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory area.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 598 of file riscv32Cpu.cpp.
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[architecture api] - Sets the concrete value of memory cells.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 568 of file riscv32Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory cell.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 561 of file riscv32Cpu.cpp.
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[architecture api] - Sets the concrete value of a register.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 607 of file riscv32Cpu.cpp.
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Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
Implements triton::arch::CpuInterface.
Definition at line 706 of file riscv32Cpu.cpp.
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Sets CPU state to Thumb mode.
Implements triton::arch::CpuInterface.
Definition at line 695 of file riscv32Cpu.cpp.
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Concrete value of f0.
Definition at line 146 of file riscv32Cpu.hpp.
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Concrete value of f1.
Definition at line 148 of file riscv32Cpu.hpp.
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Concrete value of f10.
Definition at line 166 of file riscv32Cpu.hpp.
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Concrete value of f11.
Definition at line 168 of file riscv32Cpu.hpp.
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Concrete value of f12.
Definition at line 170 of file riscv32Cpu.hpp.
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Concrete value of f13.
Definition at line 172 of file riscv32Cpu.hpp.
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Concrete value of f14.
Definition at line 174 of file riscv32Cpu.hpp.
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Concrete value of f15.
Definition at line 176 of file riscv32Cpu.hpp.
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Concrete value of f16.
Definition at line 178 of file riscv32Cpu.hpp.
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Concrete value of f17.
Definition at line 180 of file riscv32Cpu.hpp.
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Concrete value of f18.
Definition at line 182 of file riscv32Cpu.hpp.
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Concrete value of f19.
Definition at line 184 of file riscv32Cpu.hpp.
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Concrete value of f2.
Definition at line 150 of file riscv32Cpu.hpp.
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Concrete value of f20.
Definition at line 186 of file riscv32Cpu.hpp.
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Concrete value of f21.
Definition at line 188 of file riscv32Cpu.hpp.
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Concrete value of f22.
Definition at line 190 of file riscv32Cpu.hpp.
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Concrete value of f23.
Definition at line 192 of file riscv32Cpu.hpp.
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Concrete value of f24.
Definition at line 194 of file riscv32Cpu.hpp.
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Concrete value of f25.
Definition at line 196 of file riscv32Cpu.hpp.
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Concrete value of f26.
Definition at line 198 of file riscv32Cpu.hpp.
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Concrete value of f27.
Definition at line 200 of file riscv32Cpu.hpp.
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Concrete value of f28.
Definition at line 202 of file riscv32Cpu.hpp.
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Concrete value of f29.
Definition at line 204 of file riscv32Cpu.hpp.
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Concrete value of f3.
Definition at line 152 of file riscv32Cpu.hpp.
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Concrete value of f30.
Definition at line 206 of file riscv32Cpu.hpp.
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Concrete value of f31.
Definition at line 208 of file riscv32Cpu.hpp.
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Concrete value of f4.
Definition at line 154 of file riscv32Cpu.hpp.
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Concrete value of f5.
Definition at line 156 of file riscv32Cpu.hpp.
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Concrete value of f6.
Definition at line 158 of file riscv32Cpu.hpp.
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Concrete value of f7.
Definition at line 160 of file riscv32Cpu.hpp.
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Concrete value of f8.
Definition at line 162 of file riscv32Cpu.hpp.
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Concrete value of f9.
Definition at line 164 of file riscv32Cpu.hpp.
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map of address -> concrete value
item1: memory address
item2: concrete value
Definition at line 79 of file riscv32Cpu.hpp.
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Concrete value of pc.
Definition at line 210 of file riscv32Cpu.hpp.
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Concrete value of sp.
Definition at line 86 of file riscv32Cpu.hpp.
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Concrete value of x0.
Definition at line 82 of file riscv32Cpu.hpp.
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Concrete value of x1.
Definition at line 84 of file riscv32Cpu.hpp.
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Concrete value of x10.
Definition at line 102 of file riscv32Cpu.hpp.
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Concrete value of x11.
Definition at line 104 of file riscv32Cpu.hpp.
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Concrete value of x12.
Definition at line 106 of file riscv32Cpu.hpp.
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Concrete value of x13.
Definition at line 108 of file riscv32Cpu.hpp.
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Concrete value of x14.
Definition at line 110 of file riscv32Cpu.hpp.
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Concrete value of x15.
Definition at line 112 of file riscv32Cpu.hpp.
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Concrete value of x16.
Definition at line 114 of file riscv32Cpu.hpp.
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Concrete value of x17.
Definition at line 116 of file riscv32Cpu.hpp.
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Concrete value of x18.
Definition at line 118 of file riscv32Cpu.hpp.
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Concrete value of x19.
Definition at line 120 of file riscv32Cpu.hpp.
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Concrete value of x20.
Definition at line 122 of file riscv32Cpu.hpp.
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Concrete value of x21.
Definition at line 124 of file riscv32Cpu.hpp.
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Concrete value of x22.
Definition at line 126 of file riscv32Cpu.hpp.
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Concrete value of x23.
Definition at line 128 of file riscv32Cpu.hpp.
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Concrete value of x24.
Definition at line 130 of file riscv32Cpu.hpp.
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Concrete value of x25.
Definition at line 132 of file riscv32Cpu.hpp.
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Concrete value of x26.
Definition at line 134 of file riscv32Cpu.hpp.
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Concrete value of x27.
Definition at line 136 of file riscv32Cpu.hpp.
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Concrete value of x28.
Definition at line 138 of file riscv32Cpu.hpp.
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Concrete value of x29.
Definition at line 140 of file riscv32Cpu.hpp.
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Concrete value of x3.
Definition at line 88 of file riscv32Cpu.hpp.
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Concrete value of x30.
Definition at line 142 of file riscv32Cpu.hpp.
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Concrete value of x31.
Definition at line 144 of file riscv32Cpu.hpp.
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Concrete value of x4.
Definition at line 90 of file riscv32Cpu.hpp.
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Concrete value of x5.
Definition at line 92 of file riscv32Cpu.hpp.
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Concrete value of x6.
Definition at line 94 of file riscv32Cpu.hpp.
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Concrete value of x7.
Definition at line 96 of file riscv32Cpu.hpp.
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Concrete value of x8.
Definition at line 98 of file riscv32Cpu.hpp.
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Concrete value of x9.
Definition at line 100 of file riscv32Cpu.hpp.