The riscvSpecifications class defines specifications about the RV32 and RV64 CPU. More...

#include <riscvSpecifications.hpp>

Inheritance diagram for triton::arch::riscv::riscvSpecifications:

Public Member Functions
TRITON_EXPORT	riscvSpecifications (triton::arch::architecture_e)
	Constructor.

TRITON_EXPORT triton::arch::register_e	capstoneRegisterToTritonRegister64 (triton::uint32 id) const
	Converts a capstone's register id to a triton's register id for RV64.

TRITON_EXPORT triton::arch::register_e	capstoneRegisterToTritonRegister32 (triton::uint32 id) const
	Converts a capstone's register id to a triton's register id for RV32.

TRITON_EXPORT triton::uint32	capstoneInstructionToTritonInstruction (triton::uint32 id) const
	Converts a capstone's instruction id to a triton's instruction id.

TRITON_EXPORT triton::arch::riscv::insn_group_e	capstoneGroupToTritonGroup (triton::uint32 id) const
	Converts a capstone's group id to a triton's group id.

TRITON_EXPORT triton::uint32	getMemoryOperandSpecialSize (triton::uint32 id) const
	Returns memory access size if it is specified by instruction.

Protected Attributes
std::unordered_map< triton::arch::register_e, const triton::arch::Register >	id2reg
	List of registers specification available for this architecture.

std::unordered_map< std::string, triton::arch::register_e >	name2id

Detailed Description

The riscvSpecifications class defines specifications about the RV32 and RV64 CPU.

Definition at line 47 of file riscvSpecifications.hpp.

Constructor & Destructor Documentation

◆ riscvSpecifications()

triton::arch::riscv::riscvSpecifications::riscvSpecifications ( triton::arch::architecture_e arch )

Constructor.

Definition at line 22 of file riscvSpecifications.cpp.

Member Function Documentation

◆ capstoneInstructionToTritonInstruction()

triton::uint32 triton::arch::riscv::riscvSpecifications::capstoneInstructionToTritonInstruction ( triton::uint32 id ) const

Converts a capstone's instruction id to a triton's instruction id.

Definition at line 105 of file riscvSpecifications.cpp.

◆ capstoneRegisterToTritonRegister32()

triton::arch::register_e triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister32 ( triton::uint32 id ) const

Converts a capstone's register id to a triton's register id for RV32.

Definition at line 84 of file riscvSpecifications.cpp.

◆ capstoneRegisterToTritonRegister64()

triton::arch::register_e triton::arch::riscv::riscvSpecifications::capstoneRegisterToTritonRegister64 ( triton::uint32 id ) const

Converts a capstone's register id to a triton's register id for RV64.

Definition at line 63 of file riscvSpecifications.cpp.

◆ getMemoryOperandSpecialSize()

triton::uint32 triton::arch::riscv::riscvSpecifications::getMemoryOperandSpecialSize ( triton::uint32 id ) const

Returns memory access size if it is specified by instruction.

Definition at line 1209 of file riscvSpecifications.cpp.

Member Data Documentation

◆ id2reg

std::unordered_map<triton::arch::register_e, const triton::arch::Register> triton::arch::riscv::riscvSpecifications::id2reg

protected

List of registers specification available for this architecture.

Definition at line 50 of file riscvSpecifications.hpp.

◆ name2id

std::unordered_map<std::string, triton::arch::register_e> triton::arch::riscv::riscvSpecifications::name2id