libTriton version 1.0 build 1592
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riscv32Cpu.cpp
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1
2/*
3** Copyright (C) - Triton
4**
5** This program is under the terms of the Apache License 2.0.
6*/
7
8#include <algorithm>
9#include <cctype>
10#include <cstring>
11
13#include <triton/coreUtils.hpp>
14#include <triton/cpuSize.hpp>
15#include <triton/exceptions.hpp>
17#include <triton/immediate.hpp>
18#include <triton/riscv32Cpu.hpp>
19
20
21
22namespace triton {
23 namespace arch {
24 namespace riscv {
25
27 this->callbacks = callbacks;
28 this->handle = 0;
29
30 this->clear();
31 this->disassInit();
32 }
33
34
36 this->copy(other);
37 }
38
39
41 this->memory.clear();
42 if (this->handle) {
43 triton::extlibs::capstone::cs_close(&this->handle);
44 }
45 }
46
47 void riscv32Cpu::disassInit(void) {
48 if (this->handle) {
49 triton::extlibs::capstone::cs_close(&this->handle);
50 }
51
52 // CS_MODE_RISCV32 | CS_MODE_RISCVC
53 auto rv_mode = static_cast<triton::extlibs::capstone::cs_mode>((1 << 0) | (1 << 2));
54 if (triton::extlibs::capstone::cs_open(triton::extlibs::capstone::CS_ARCH_RISCV, rv_mode, &this->handle) != triton::extlibs::capstone::CS_ERR_OK)
55 throw triton::exceptions::Disassembly("riscv32Cpu::disassInit(): Cannot open capstone.");
56
57 triton::extlibs::capstone::cs_option(this->handle, triton::extlibs::capstone::CS_OPT_DETAIL, triton::extlibs::capstone::CS_OPT_ON);
58 }
59
60
61 void riscv32Cpu::copy(const riscv32Cpu& other) {
62 this->callbacks = other.callbacks;
63 this->memory = other.memory;
64
65 std::memcpy(this->x0, other.x0, sizeof(this->x0));
66 std::memcpy(this->x1, other.x1, sizeof(this->x1));
67 std::memcpy(this->sp, other.sp, sizeof(this->sp));
68 std::memcpy(this->x3, other.x3, sizeof(this->x3));
69 std::memcpy(this->x4, other.x4, sizeof(this->x4));
70 std::memcpy(this->x5, other.x5, sizeof(this->x5));
71 std::memcpy(this->x6, other.x6, sizeof(this->x6));
72 std::memcpy(this->x7, other.x7, sizeof(this->x7));
73 std::memcpy(this->x8, other.x8, sizeof(this->x8));
74 std::memcpy(this->x9, other.x9, sizeof(this->x9));
75 std::memcpy(this->x10, other.x10, sizeof(this->x10));
76 std::memcpy(this->x11, other.x11, sizeof(this->x11));
77 std::memcpy(this->x12, other.x12, sizeof(this->x12));
78 std::memcpy(this->x13, other.x13, sizeof(this->x13));
79 std::memcpy(this->x14, other.x14, sizeof(this->x14));
80 std::memcpy(this->x15, other.x15, sizeof(this->x15));
81 std::memcpy(this->x16, other.x16, sizeof(this->x16));
82 std::memcpy(this->x17, other.x17, sizeof(this->x17));
83 std::memcpy(this->x18, other.x18, sizeof(this->x18));
84 std::memcpy(this->x19, other.x19, sizeof(this->x19));
85 std::memcpy(this->x20, other.x20, sizeof(this->x20));
86 std::memcpy(this->x21, other.x21, sizeof(this->x21));
87 std::memcpy(this->x22, other.x22, sizeof(this->x22));
88 std::memcpy(this->x23, other.x23, sizeof(this->x23));
89 std::memcpy(this->x24, other.x24, sizeof(this->x24));
90 std::memcpy(this->x25, other.x25, sizeof(this->x25));
91 std::memcpy(this->x26, other.x26, sizeof(this->x26));
92 std::memcpy(this->x27, other.x27, sizeof(this->x27));
93 std::memcpy(this->x28, other.x28, sizeof(this->x28));
94 std::memcpy(this->x29, other.x29, sizeof(this->x29));
95 std::memcpy(this->x30, other.x30, sizeof(this->x30));
96 std::memcpy(this->x31, other.x31, sizeof(this->x31));
97 std::memcpy(this->pc, other.pc, sizeof(this->pc));
98 std::memcpy(this->f0, other.f0, sizeof(this->f0));
99 std::memcpy(this->f1, other.f1, sizeof(this->f1));
100 std::memcpy(this->f2, other.f2, sizeof(this->f2));
101 std::memcpy(this->f3, other.f3, sizeof(this->f3));
102 std::memcpy(this->f4, other.f4, sizeof(this->f4));
103 std::memcpy(this->f5, other.f5, sizeof(this->f5));
104 std::memcpy(this->f6, other.f6, sizeof(this->f6));
105 std::memcpy(this->f7, other.f7, sizeof(this->f7));
106 std::memcpy(this->f8, other.f8, sizeof(this->f8));
107 std::memcpy(this->f9, other.f9, sizeof(this->f9));
108 std::memcpy(this->f10, other.f10, sizeof(this->f10));
109 std::memcpy(this->f11, other.f11, sizeof(this->f11));
110 std::memcpy(this->f12, other.f12, sizeof(this->f12));
111 std::memcpy(this->f13, other.f13, sizeof(this->f13));
112 std::memcpy(this->f14, other.f14, sizeof(this->f14));
113 std::memcpy(this->f15, other.f15, sizeof(this->f15));
114 std::memcpy(this->f16, other.f16, sizeof(this->f16));
115 std::memcpy(this->f17, other.f17, sizeof(this->f17));
116 std::memcpy(this->f18, other.f18, sizeof(this->f18));
117 std::memcpy(this->f19, other.f19, sizeof(this->f19));
118 std::memcpy(this->f20, other.f20, sizeof(this->f20));
119 std::memcpy(this->f21, other.f21, sizeof(this->f21));
120 std::memcpy(this->f22, other.f22, sizeof(this->f22));
121 std::memcpy(this->f23, other.f23, sizeof(this->f23));
122 std::memcpy(this->f24, other.f24, sizeof(this->f24));
123 std::memcpy(this->f25, other.f25, sizeof(this->f25));
124 std::memcpy(this->f26, other.f26, sizeof(this->f26));
125 std::memcpy(this->f27, other.f27, sizeof(this->f27));
126 std::memcpy(this->f28, other.f28, sizeof(this->f28));
127 std::memcpy(this->f29, other.f29, sizeof(this->f29));
128 std::memcpy(this->f30, other.f30, sizeof(this->f30));
129 std::memcpy(this->f31, other.f31, sizeof(this->f31));
130 }
131
132
133 void riscv32Cpu::clear(void) {
134 /* Clear memory */
135 this->memory.clear();
136
137 /* Clear registers */
138 std::memset(this->x0, 0x00, sizeof(this->x0));
139 std::memset(this->x1, 0x00, sizeof(this->x1));
140 std::memset(this->sp, 0x00, sizeof(this->sp));
141 std::memset(this->x3, 0x00, sizeof(this->x3));
142 std::memset(this->x4, 0x00, sizeof(this->x4));
143 std::memset(this->x5, 0x00, sizeof(this->x5));
144 std::memset(this->x6, 0x00, sizeof(this->x6));
145 std::memset(this->x7, 0x00, sizeof(this->x7));
146 std::memset(this->x8, 0x00, sizeof(this->x8));
147 std::memset(this->x9, 0x00, sizeof(this->x9));
148 std::memset(this->x10, 0x00, sizeof(this->x10));
149 std::memset(this->x11, 0x00, sizeof(this->x11));
150 std::memset(this->x12, 0x00, sizeof(this->x12));
151 std::memset(this->x13, 0x00, sizeof(this->x13));
152 std::memset(this->x14, 0x00, sizeof(this->x14));
153 std::memset(this->x15, 0x00, sizeof(this->x15));
154 std::memset(this->x16, 0x00, sizeof(this->x16));
155 std::memset(this->x17, 0x00, sizeof(this->x17));
156 std::memset(this->x18, 0x00, sizeof(this->x18));
157 std::memset(this->x19, 0x00, sizeof(this->x19));
158 std::memset(this->x20, 0x00, sizeof(this->x20));
159 std::memset(this->x21, 0x00, sizeof(this->x21));
160 std::memset(this->x22, 0x00, sizeof(this->x22));
161 std::memset(this->x23, 0x00, sizeof(this->x23));
162 std::memset(this->x24, 0x00, sizeof(this->x24));
163 std::memset(this->x25, 0x00, sizeof(this->x25));
164 std::memset(this->x26, 0x00, sizeof(this->x26));
165 std::memset(this->x27, 0x00, sizeof(this->x27));
166 std::memset(this->x28, 0x00, sizeof(this->x28));
167 std::memset(this->x29, 0x00, sizeof(this->x29));
168 std::memset(this->x30, 0x00, sizeof(this->x30));
169 std::memset(this->x31, 0x00, sizeof(this->x31));
170 std::memset(this->pc, 0x00, sizeof(this->pc));
171 std::memset(this->f0, 0x00, sizeof(this->f0));
172 std::memset(this->f1, 0x00, sizeof(this->f1));
173 std::memset(this->f2, 0x00, sizeof(this->f2));
174 std::memset(this->f3, 0x00, sizeof(this->f3));
175 std::memset(this->f4, 0x00, sizeof(this->f4));
176 std::memset(this->f5, 0x00, sizeof(this->f5));
177 std::memset(this->f6, 0x00, sizeof(this->f6));
178 std::memset(this->f7, 0x00, sizeof(this->f7));
179 std::memset(this->f8, 0x00, sizeof(this->f8));
180 std::memset(this->f9, 0x00, sizeof(this->f9));
181 std::memset(this->f10, 0x00, sizeof(this->f10));
182 std::memset(this->f11, 0x00, sizeof(this->f11));
183 std::memset(this->f12, 0x00, sizeof(this->f12));
184 std::memset(this->f13, 0x00, sizeof(this->f13));
185 std::memset(this->f14, 0x00, sizeof(this->f14));
186 std::memset(this->f15, 0x00, sizeof(this->f15));
187 std::memset(this->f16, 0x00, sizeof(this->f16));
188 std::memset(this->f17, 0x00, sizeof(this->f17));
189 std::memset(this->f18, 0x00, sizeof(this->f18));
190 std::memset(this->f19, 0x00, sizeof(this->f19));
191 std::memset(this->f20, 0x00, sizeof(this->f20));
192 std::memset(this->f21, 0x00, sizeof(this->f21));
193 std::memset(this->f22, 0x00, sizeof(this->f22));
194 std::memset(this->f23, 0x00, sizeof(this->f23));
195 std::memset(this->f24, 0x00, sizeof(this->f24));
196 std::memset(this->f25, 0x00, sizeof(this->f25));
197 std::memset(this->f26, 0x00, sizeof(this->f26));
198 std::memset(this->f27, 0x00, sizeof(this->f27));
199 std::memset(this->f28, 0x00, sizeof(this->f28));
200 std::memset(this->f29, 0x00, sizeof(this->f29));
201 std::memset(this->f30, 0x00, sizeof(this->f30));
202 std::memset(this->f31, 0x00, sizeof(this->f31));
203 }
204
205
207 this->copy(other);
208 return *this;
209 }
210
211
215
216
218 return (this->isGPR(regId) || this->isFPU(regId) || regId == triton::arch::ID_REG_RV32_PC);
219 }
220
221
223 return (this->isFlag(regId) || this->isRegister(regId));
224 }
225
226
228 return ((regId >= triton::arch::ID_REG_RV32_X0 && regId <= triton::arch::ID_REG_RV32_X31) ? true : false);
229 }
230
231
233 return ((regId >= triton::arch::ID_REG_RV32_F0 && regId <= triton::arch::ID_REG_RV32_F31) ? true : false);
234 }
235
236
238 return false;
239 }
240
241
245
246
250
251
255
256
257 const std::unordered_map<triton::arch::register_e, const triton::arch::Register>& riscv32Cpu::getAllRegisters(void) const {
258 return this->id2reg;
259 }
260
261 const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>& riscv32Cpu::getConcreteMemory(void) const {
262 return this->memory;
263 }
264
265 std::set<const triton::arch::Register*> riscv32Cpu::getParentRegisters(void) const {
266 std::set<const triton::arch::Register*> ret;
267
268 for (const auto& kv: this->id2reg) {
269 auto regId = kv.first;
270 const auto& reg = kv.second;
271
272 /* Add GPR */
273 if (reg.getSize() == this->gprSize())
274 ret.insert(&reg);
275
276 /* Add FPU */
277 else if (this->isFPU(regId))
278 ret.insert(&reg);
279 }
280
281 return ret;
282 }
283
284
286 try {
287 return this->id2reg.at(id);
288 } catch (const std::out_of_range&) {
289 throw triton::exceptions::Cpu("riscv32Cpu::getRegister(): Invalid register for this architecture.");
290 }
291 }
292
293
294 const triton::arch::Register& riscv32Cpu::getRegister(const std::string& name) const {
295 std::string lower = name;
296 std::transform(lower.begin(), lower.end(), lower.begin(), [](unsigned char c){ return std::tolower(c); });
297 try {
298 return this->getRegister(this->name2id.at(lower));
299 } catch (const std::out_of_range&) {
300 throw triton::exceptions::Cpu("riscv32Cpu::getRegister(): Invalid register for this architecture.");
301 }
302 }
303
304
308
309
313
314
316 return this->getRegister(this->pcId);
317 }
318
319
321 return this->getRegister(this->spId);
322 }
323
325
326 triton::extlibs::capstone::cs_insn* insn;
327 triton::usize count = 0;
328 triton::uint32 size = 0;
329
330 /* Check if the opcode and opcode' size are defined */
331 if (inst.getOpcode() == nullptr || inst.getSize() == 0)
332 throw triton::exceptions::Disassembly("riscv32Cpu::disassembly(): Opcode and opcodeSize must be definied.");
333
334 /* Clear instructicon's operands if alredy defined */
335 inst.operands.clear();
336
337 /* Update instruction address if undefined */
338 if (!inst.getAddress()) {
339 inst.setAddress(static_cast<triton::uint32>(this->getConcreteRegisterValue(this->getProgramCounter())));
340 }
341
342 /* Let's disass and build our operands */
343 count = triton::extlibs::capstone::cs_disasm(this->handle, inst.getOpcode(), inst.getSize(), inst.getAddress(), 0, &insn);
344 if (count > 0) {
345 /* Detail information */
346 triton::extlibs::capstone::cs_detail* detail = insn->detail;
347
348 /* Init the disassembly */
349 std::stringstream str;
350
351 str << insn[0].mnemonic;
352 if (detail->riscv.op_count)
353 str << " " << insn[0].op_str;
354
355 inst.setDisassembly(str.str());
356
357 /* Refine the size */
358 inst.setSize(insn[0].size);
359
360 /* Init the instruction's type */
361 inst.setType(this->capstoneInstructionToTritonInstruction(insn[0].id));
362
363 /* Set architecture */
364 inst.setArchitecture(triton::arch::ARCH_RV32);
365
366 /* Init operands */
367 for (triton::uint32 n = 0; n < detail->riscv.op_count; n++) {
368 triton::extlibs::capstone::cs_riscv_op* op = &(detail->riscv.operands[n]);
369
370 switch(op->type) {
371
372 case triton::extlibs::capstone::RISCV_OP_IMM: {
373 triton::arch::Immediate imm(op->imm, size ? size : triton::size::dword);
374 if (static_cast<triton::uint32>(op->imm) > imm.getValue()) {
375 imm = Immediate();
376 imm.setValue(op->imm, 0); /* By setting 0 as size, we automatically identify the size of the value */
377 }
378
379 inst.operands.push_back(triton::arch::OperandWrapper(imm));
380 break;
381 }
382
383 case triton::extlibs::capstone::RISCV_OP_MEM: {
385
386 /* Set the size of the memory access */
387 size = this->getMemoryOperandSpecialSize(inst.getType());
388 mem.setBits(size ? ((size * triton::bitsize::byte) - 1) : triton::bitsize::dword - 1, 0);
389
390 /* Set address calculation units */
391 triton::arch::Register base(*this, this->capstoneRegisterToTritonRegister32(op->mem.base));
392
393 triton::uint32 immsize = (
394 this->isRegisterValid(base.getId()) ? base.getSize() :
395 this->gprSize()
396 );
397
398 triton::arch::Immediate disp(op->mem.disp, immsize);
399
400 mem.setBaseRegister(base);
401 mem.setDisplacement(disp);
402
403 inst.operands.push_back(triton::arch::OperandWrapper(mem));
404 break;
405 }
406
407 case triton::extlibs::capstone::RISCV_OP_REG: {
409 break;
410 }
411
412 default:
413 throw triton::exceptions::Disassembly("riscv32Cpu::disassembly(): Invalid operand.");
414 } // switch
415 } // for operand
416
417 /* Set branch */
418 if (detail->groups_count > 0) {
419 for (triton::uint32 n = 0; n < detail->groups_count; n++) {
420 if (detail->groups[n] == triton::extlibs::capstone::RISCV_GRP_JUMP)
421 inst.setBranch(true);
422 if (detail->groups[n] == triton::extlibs::capstone::RISCV_GRP_JUMP ||
423 detail->groups[n] == triton::extlibs::capstone::RISCV_GRP_CALL ||
424 detail->groups[n] == triton::extlibs::capstone::RISCV_GRP_RET)
425 inst.setControlFlow(true);
426 }
427 }
428
429 /* Free capstone stuffs */
430 triton::extlibs::capstone::cs_free(insn, count);
431 }
432 else
433 throw triton::exceptions::Disassembly("riscv32Cpu::disassembly(): Failed to disassemble the given code.");
434 }
435
436
438 if (execCallbacks && this->callbacks)
440
441 auto it = this->memory.find(addr);
442 if (it == this->memory.end()) {
443 return 0x00;
444 }
445
446 return it->second;
447 }
448
449
451 triton::uint512 ret = 0;
452 triton::uint64 addr = 0;
453 triton::uint32 size = 0;
454
455 if (execCallbacks && this->callbacks)
457
458 addr = mem.getAddress();
459 size = mem.getSize();
460
461 if (size == 0 || size > triton::size::dqqword)
462 throw triton::exceptions::Cpu("riscv32Cpu::getConcreteMemoryValue(): Invalid size memory.");
463
464 for (triton::sint32 i = size-1; i >= 0; i--)
465 ret = ((ret << triton::bitsize::byte) | this->getConcreteMemoryValue(addr+i, false));
466
467 return ret;
468 }
469
470
471 std::vector<triton::uint8> riscv32Cpu::getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks) const {
472 std::vector<triton::uint8> area;
473
474 for (triton::usize index = 0; index < size; index++)
475 area.push_back(this->getConcreteMemoryValue(baseAddr+index, execCallbacks));
476
477 return area;
478 }
479
480
482 triton::uint512 value = 0;
483
484 if (execCallbacks && this->callbacks)
486 switch (reg.getId()) {
487 case triton::arch::ID_REG_RV32_X0: return 0;
488 case triton::arch::ID_REG_RV32_X1: return (*((triton::uint32*)(this->x1)));
489 case triton::arch::ID_REG_RV32_SP: return (*((triton::uint32*)(this->sp)));
490 case triton::arch::ID_REG_RV32_X3: return (*((triton::uint32*)(this->x3)));
491 case triton::arch::ID_REG_RV32_X4: return (*((triton::uint32*)(this->x4)));
492 case triton::arch::ID_REG_RV32_X5: return (*((triton::uint32*)(this->x5)));
493 case triton::arch::ID_REG_RV32_X6: return (*((triton::uint32*)(this->x6)));
494 case triton::arch::ID_REG_RV32_X7: return (*((triton::uint32*)(this->x7)));
495 case triton::arch::ID_REG_RV32_X8: return (*((triton::uint32*)(this->x8)));
496 case triton::arch::ID_REG_RV32_X9: return (*((triton::uint32*)(this->x9)));
497 case triton::arch::ID_REG_RV32_X10: return (*((triton::uint32*)(this->x10)));
498 case triton::arch::ID_REG_RV32_X11: return (*((triton::uint32*)(this->x11)));
499 case triton::arch::ID_REG_RV32_X12: return (*((triton::uint32*)(this->x12)));
500 case triton::arch::ID_REG_RV32_X13: return (*((triton::uint32*)(this->x13)));
501 case triton::arch::ID_REG_RV32_X14: return (*((triton::uint32*)(this->x14)));
502 case triton::arch::ID_REG_RV32_X15: return (*((triton::uint32*)(this->x15)));
503 case triton::arch::ID_REG_RV32_X16: return (*((triton::uint32*)(this->x16)));
504 case triton::arch::ID_REG_RV32_X17: return (*((triton::uint32*)(this->x17)));
505 case triton::arch::ID_REG_RV32_X18: return (*((triton::uint32*)(this->x18)));
506 case triton::arch::ID_REG_RV32_X19: return (*((triton::uint32*)(this->x19)));
507 case triton::arch::ID_REG_RV32_X20: return (*((triton::uint32*)(this->x20)));
508 case triton::arch::ID_REG_RV32_X21: return (*((triton::uint32*)(this->x21)));
509 case triton::arch::ID_REG_RV32_X22: return (*((triton::uint32*)(this->x22)));
510 case triton::arch::ID_REG_RV32_X23: return (*((triton::uint32*)(this->x23)));
511 case triton::arch::ID_REG_RV32_X24: return (*((triton::uint32*)(this->x24)));
512 case triton::arch::ID_REG_RV32_X25: return (*((triton::uint32*)(this->x25)));
513 case triton::arch::ID_REG_RV32_X26: return (*((triton::uint32*)(this->x26)));
514 case triton::arch::ID_REG_RV32_X27: return (*((triton::uint32*)(this->x27)));
515 case triton::arch::ID_REG_RV32_X28: return (*((triton::uint32*)(this->x28)));
516 case triton::arch::ID_REG_RV32_X29: return (*((triton::uint32*)(this->x29)));
517 case triton::arch::ID_REG_RV32_X30: return (*((triton::uint32*)(this->x30)));
518 case triton::arch::ID_REG_RV32_X31: return (*((triton::uint32*)(this->x31)));
519 case triton::arch::ID_REG_RV32_PC: return (*((triton::uint32*)(this->pc)));
520 case triton::arch::ID_REG_RV32_F0: return (*((triton::uint32*)(this->f0)));
521 case triton::arch::ID_REG_RV32_F1: return (*((triton::uint32*)(this->f1)));
522 case triton::arch::ID_REG_RV32_F2: return (*((triton::uint32*)(this->f2)));
523 case triton::arch::ID_REG_RV32_F3: return (*((triton::uint32*)(this->f3)));
524 case triton::arch::ID_REG_RV32_F4: return (*((triton::uint32*)(this->f4)));
525 case triton::arch::ID_REG_RV32_F5: return (*((triton::uint32*)(this->f5)));
526 case triton::arch::ID_REG_RV32_F6: return (*((triton::uint32*)(this->f6)));
527 case triton::arch::ID_REG_RV32_F7: return (*((triton::uint32*)(this->f7)));
528 case triton::arch::ID_REG_RV32_F8: return (*((triton::uint32*)(this->f8)));
529 case triton::arch::ID_REG_RV32_F9: return (*((triton::uint32*)(this->f9)));
530 case triton::arch::ID_REG_RV32_F10: return (*((triton::uint32*)(this->f10)));
531 case triton::arch::ID_REG_RV32_F11: return (*((triton::uint32*)(this->f11)));
532 case triton::arch::ID_REG_RV32_F12: return (*((triton::uint32*)(this->f12)));
533 case triton::arch::ID_REG_RV32_F13: return (*((triton::uint32*)(this->f13)));
534 case triton::arch::ID_REG_RV32_F14: return (*((triton::uint32*)(this->f14)));
535 case triton::arch::ID_REG_RV32_F15: return (*((triton::uint32*)(this->f15)));
536 case triton::arch::ID_REG_RV32_F16: return (*((triton::uint32*)(this->f16)));
537 case triton::arch::ID_REG_RV32_F17: return (*((triton::uint32*)(this->f17)));
538 case triton::arch::ID_REG_RV32_F18: return (*((triton::uint32*)(this->f18)));
539 case triton::arch::ID_REG_RV32_F19: return (*((triton::uint32*)(this->f19)));
540 case triton::arch::ID_REG_RV32_F20: return (*((triton::uint32*)(this->f20)));
541 case triton::arch::ID_REG_RV32_F21: return (*((triton::uint32*)(this->f21)));
542 case triton::arch::ID_REG_RV32_F22: return (*((triton::uint32*)(this->f22)));
543 case triton::arch::ID_REG_RV32_F23: return (*((triton::uint32*)(this->f23)));
544 case triton::arch::ID_REG_RV32_F24: return (*((triton::uint32*)(this->f24)));
545 case triton::arch::ID_REG_RV32_F25: return (*((triton::uint32*)(this->f25)));
546 case triton::arch::ID_REG_RV32_F26: return (*((triton::uint32*)(this->f26)));
547 case triton::arch::ID_REG_RV32_F27: return (*((triton::uint32*)(this->f27)));
548 case triton::arch::ID_REG_RV32_F28: return (*((triton::uint32*)(this->f28)));
549 case triton::arch::ID_REG_RV32_F29: return (*((triton::uint32*)(this->f29)));
550 case triton::arch::ID_REG_RV32_F30: return (*((triton::uint32*)(this->f30)));
551 case triton::arch::ID_REG_RV32_F31: return (*((triton::uint32*)(this->f31)));
552
553 default:
554 throw triton::exceptions::Cpu("riscv32Cpu::getConcreteRegisterValue(): Invalid register.");
555 }
556
557 return value;
558 }
559
560
562 if (execCallbacks && this->callbacks)
564 this->memory[addr] = value;
565 }
566
567
568 void riscv32Cpu::setConcreteMemoryValue(const triton::arch::MemoryAccess& mem, const triton::uint512& value, bool execCallbacks) {
569 triton::uint64 addr = mem.getAddress();
570 triton::uint32 size = mem.getSize();
571 triton::uint512 cv = value;
572
573 if (cv > mem.getMaxValue())
574 throw triton::exceptions::Register("riscv32Cpu::setConcreteMemoryValue(): You cannot set this concrete value (too big) to this memory access.");
575
576 if (size == 0 || size > triton::size::dqqword)
577 throw triton::exceptions::Cpu("riscv32Cpu::setConcreteMemoryValue(): Invalid size memory.");
578
579 if (execCallbacks && this->callbacks)
581
582 for (triton::uint32 i = 0; i < size; i++) {
583 this->memory[addr+i] = static_cast<triton::uint8>((cv & 0xff));
584 cv >>= 8;
585 }
586 }
587
588
589 void riscv32Cpu::setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector<triton::uint8>& values, bool execCallbacks) {
590 // Pre-reserving the memory. We modified the original robin_map to not force rehash on reserve.
591 this->memory.reserve(values.size() + this->memory.size());
592 for (triton::usize index = 0; index < values.size(); index++) {
593 this->setConcreteMemoryValue(baseAddr+index, values[index], execCallbacks);
594 }
595 }
596
597
598 void riscv32Cpu::setConcreteMemoryAreaValue(triton::uint64 baseAddr, const void* area, triton::usize size, bool execCallbacks) {
599 // Pre-reserving the memory. We modified the original robin_map to not force rehash on every reserve if not needed.
600 this->memory.reserve(size + this->memory.size());
601 for (triton::usize index = 0; index < size; index++) {
602 this->setConcreteMemoryValue(baseAddr+index, reinterpret_cast<const triton::uint8*>(area)[index], execCallbacks);
603 }
604 }
605
606
607 void riscv32Cpu::setConcreteRegisterValue(const triton::arch::Register& reg, const triton::uint512& value, bool execCallbacks) {
608 if (value > reg.getMaxValue())
609 throw triton::exceptions::Register("riscv32Cpu::setConcreteRegisterValue(): You cannot set this concrete value (too big) to this register.");
610
611 if (execCallbacks && this->callbacks)
613
614 switch (reg.getId()) {
615 case triton::arch::ID_REG_RV32_X0: break; // Always zero, just do nothing
616 case triton::arch::ID_REG_RV32_X1: (*((triton::uint32*)(this->x1))) = static_cast<triton::uint32>(value); break;
617 case triton::arch::ID_REG_RV32_SP: (*((triton::uint32*)(this->sp))) = static_cast<triton::uint32>(value); break;
618 case triton::arch::ID_REG_RV32_X3: (*((triton::uint32*)(this->x3))) = static_cast<triton::uint32>(value); break;
619 case triton::arch::ID_REG_RV32_X4: (*((triton::uint32*)(this->x4))) = static_cast<triton::uint32>(value); break;
620 case triton::arch::ID_REG_RV32_X5: (*((triton::uint32*)(this->x5))) = static_cast<triton::uint32>(value); break;
621 case triton::arch::ID_REG_RV32_X6: (*((triton::uint32*)(this->x6))) = static_cast<triton::uint32>(value); break;
622 case triton::arch::ID_REG_RV32_X7: (*((triton::uint32*)(this->x7))) = static_cast<triton::uint32>(value); break;
623 case triton::arch::ID_REG_RV32_X8: (*((triton::uint32*)(this->x8))) = static_cast<triton::uint32>(value); break;
624 case triton::arch::ID_REG_RV32_X9: (*((triton::uint32*)(this->x9))) = static_cast<triton::uint32>(value); break;
625 case triton::arch::ID_REG_RV32_X10: (*((triton::uint32*)(this->x10))) = static_cast<triton::uint32>(value); break;
626 case triton::arch::ID_REG_RV32_X11: (*((triton::uint32*)(this->x11))) = static_cast<triton::uint32>(value); break;
627 case triton::arch::ID_REG_RV32_X12: (*((triton::uint32*)(this->x12))) = static_cast<triton::uint32>(value); break;
628 case triton::arch::ID_REG_RV32_X13: (*((triton::uint32*)(this->x13))) = static_cast<triton::uint32>(value); break;
629 case triton::arch::ID_REG_RV32_X14: (*((triton::uint32*)(this->x14))) = static_cast<triton::uint32>(value); break;
630 case triton::arch::ID_REG_RV32_X15: (*((triton::uint32*)(this->x15))) = static_cast<triton::uint32>(value); break;
631 case triton::arch::ID_REG_RV32_X16: (*((triton::uint32*)(this->x16))) = static_cast<triton::uint32>(value); break;
632 case triton::arch::ID_REG_RV32_X17: (*((triton::uint32*)(this->x17))) = static_cast<triton::uint32>(value); break;
633 case triton::arch::ID_REG_RV32_X18: (*((triton::uint32*)(this->x18))) = static_cast<triton::uint32>(value); break;
634 case triton::arch::ID_REG_RV32_X19: (*((triton::uint32*)(this->x19))) = static_cast<triton::uint32>(value); break;
635 case triton::arch::ID_REG_RV32_X20: (*((triton::uint32*)(this->x20))) = static_cast<triton::uint32>(value); break;
636 case triton::arch::ID_REG_RV32_X21: (*((triton::uint32*)(this->x21))) = static_cast<triton::uint32>(value); break;
637 case triton::arch::ID_REG_RV32_X22: (*((triton::uint32*)(this->x22))) = static_cast<triton::uint32>(value); break;
638 case triton::arch::ID_REG_RV32_X23: (*((triton::uint32*)(this->x23))) = static_cast<triton::uint32>(value); break;
639 case triton::arch::ID_REG_RV32_X24: (*((triton::uint32*)(this->x24))) = static_cast<triton::uint32>(value); break;
640 case triton::arch::ID_REG_RV32_X25: (*((triton::uint32*)(this->x25))) = static_cast<triton::uint32>(value); break;
641 case triton::arch::ID_REG_RV32_X26: (*((triton::uint32*)(this->x26))) = static_cast<triton::uint32>(value); break;
642 case triton::arch::ID_REG_RV32_X27: (*((triton::uint32*)(this->x27))) = static_cast<triton::uint32>(value); break;
643 case triton::arch::ID_REG_RV32_X28: (*((triton::uint32*)(this->x28))) = static_cast<triton::uint32>(value); break;
644 case triton::arch::ID_REG_RV32_X29: (*((triton::uint32*)(this->x29))) = static_cast<triton::uint32>(value); break;
645 case triton::arch::ID_REG_RV32_X30: (*((triton::uint32*)(this->x30))) = static_cast<triton::uint32>(value); break;
646 case triton::arch::ID_REG_RV32_X31: (*((triton::uint32*)(this->x31))) = static_cast<triton::uint32>(value); break;
647 case triton::arch::ID_REG_RV32_PC: (*((triton::uint32*)(this->pc))) = static_cast<triton::uint32>(value); break;
648
649 case triton::arch::ID_REG_RV32_F0: (*((triton::uint32*)(this->f0))) = static_cast<triton::uint32>(value); break;
650 case triton::arch::ID_REG_RV32_F1: (*((triton::uint32*)(this->f1))) = static_cast<triton::uint32>(value); break;
651 case triton::arch::ID_REG_RV32_F2: (*((triton::uint32*)(this->f2))) = static_cast<triton::uint32>(value); break;
652 case triton::arch::ID_REG_RV32_F3: (*((triton::uint32*)(this->f3))) = static_cast<triton::uint32>(value); break;
653 case triton::arch::ID_REG_RV32_F4: (*((triton::uint32*)(this->f4))) = static_cast<triton::uint32>(value); break;
654 case triton::arch::ID_REG_RV32_F5: (*((triton::uint32*)(this->f5))) = static_cast<triton::uint32>(value); break;
655 case triton::arch::ID_REG_RV32_F6: (*((triton::uint32*)(this->f6))) = static_cast<triton::uint32>(value); break;
656 case triton::arch::ID_REG_RV32_F7: (*((triton::uint32*)(this->f7))) = static_cast<triton::uint32>(value); break;
657 case triton::arch::ID_REG_RV32_F8: (*((triton::uint32*)(this->f8))) = static_cast<triton::uint32>(value); break;
658 case triton::arch::ID_REG_RV32_F9: (*((triton::uint32*)(this->f9))) = static_cast<triton::uint32>(value); break;
659 case triton::arch::ID_REG_RV32_F10: (*((triton::uint32*)(this->f10))) = static_cast<triton::uint32>(value); break;
660 case triton::arch::ID_REG_RV32_F11: (*((triton::uint32*)(this->f11))) = static_cast<triton::uint32>(value); break;
661 case triton::arch::ID_REG_RV32_F12: (*((triton::uint32*)(this->f12))) = static_cast<triton::uint32>(value); break;
662 case triton::arch::ID_REG_RV32_F13: (*((triton::uint32*)(this->f13))) = static_cast<triton::uint32>(value); break;
663 case triton::arch::ID_REG_RV32_F14: (*((triton::uint32*)(this->f14))) = static_cast<triton::uint32>(value); break;
664 case triton::arch::ID_REG_RV32_F15: (*((triton::uint32*)(this->f15))) = static_cast<triton::uint32>(value); break;
665 case triton::arch::ID_REG_RV32_F16: (*((triton::uint32*)(this->f16))) = static_cast<triton::uint32>(value); break;
666 case triton::arch::ID_REG_RV32_F17: (*((triton::uint32*)(this->f17))) = static_cast<triton::uint32>(value); break;
667 case triton::arch::ID_REG_RV32_F18: (*((triton::uint32*)(this->f18))) = static_cast<triton::uint32>(value); break;
668 case triton::arch::ID_REG_RV32_F19: (*((triton::uint32*)(this->f19))) = static_cast<triton::uint32>(value); break;
669 case triton::arch::ID_REG_RV32_F20: (*((triton::uint32*)(this->f20))) = static_cast<triton::uint32>(value); break;
670 case triton::arch::ID_REG_RV32_F21: (*((triton::uint32*)(this->f21))) = static_cast<triton::uint32>(value); break;
671 case triton::arch::ID_REG_RV32_F22: (*((triton::uint32*)(this->f22))) = static_cast<triton::uint32>(value); break;
672 case triton::arch::ID_REG_RV32_F23: (*((triton::uint32*)(this->f23))) = static_cast<triton::uint32>(value); break;
673 case triton::arch::ID_REG_RV32_F24: (*((triton::uint32*)(this->f24))) = static_cast<triton::uint32>(value); break;
674 case triton::arch::ID_REG_RV32_F25: (*((triton::uint32*)(this->f25))) = static_cast<triton::uint32>(value); break;
675 case triton::arch::ID_REG_RV32_F26: (*((triton::uint32*)(this->f26))) = static_cast<triton::uint32>(value); break;
676 case triton::arch::ID_REG_RV32_F27: (*((triton::uint32*)(this->f27))) = static_cast<triton::uint32>(value); break;
677 case triton::arch::ID_REG_RV32_F28: (*((triton::uint32*)(this->f28))) = static_cast<triton::uint32>(value); break;
678 case triton::arch::ID_REG_RV32_F29: (*((triton::uint32*)(this->f29))) = static_cast<triton::uint32>(value); break;
679 case triton::arch::ID_REG_RV32_F30: (*((triton::uint32*)(this->f30))) = static_cast<triton::uint32>(value); break;
680 case triton::arch::ID_REG_RV32_F31: (*((triton::uint32*)(this->f31))) = static_cast<triton::uint32>(value); break;
681
682 default:
683 throw triton::exceptions::Cpu("riscv32Cpu:setConcreteRegisterValue(): Invalid register.");
684
685 }
686 }
687
688
689 bool riscv32Cpu::isThumb(void) const {
690 /* There is no thumb mode in RV */
691 return false;
692 }
693
694
695 void riscv32Cpu::setThumb(bool state) {
696 /* There is no thumb mode in RV */
697 }
698
699
701 /* There is no exclusive memory access support in RV */
702 return false;
703 }
704
705
707 /* There is no exclusive memory access support in RV */
708 }
709
710
714
715
717 for (triton::usize index = 0; index < size; index++) {
718 if (this->memory.find(baseAddr + index) == this->memory.end()) {
719 return false;
720 }
721 }
722 return true;
723 }
724
725
729
730
732 for (triton::usize index = 0; index < size; index++) {
733 if (this->memory.find(baseAddr + index) != this->memory.end()) {
734 this->memory.erase(baseAddr + index);
735 }
736 }
737 }
738
739 }; /* riscv namespace */
740 }; /* arch namespace */
741}; /* triton namespace */
TRITON_EXPORT triton::uint512 getMaxValue(void) const
Returns the max possible value of the bitvector.
TRITON_EXPORT void setBits(triton::uint32 high, triton::uint32 low)
Sets the bits (high, low) position.
This class is used to represent an immediate.
Definition immediate.hpp:37
This class is used to represent an instruction.
TRITON_EXPORT triton::uint32 getSize(void) const
Returns the size of the instruction.
TRITON_EXPORT void setDisassembly(const std::string &str)
Sets the disassembly of the instruction.
TRITON_EXPORT const triton::uint8 * getOpcode(void) const
Returns the opcode of the instruction.
TRITON_EXPORT void setType(triton::uint32 type)
Sets the type of the instruction.
TRITON_EXPORT void setAddress(triton::uint64 addr)
Sets the address of the instruction.
TRITON_EXPORT triton::uint32 getType(void) const
Returns the type of the instruction.
TRITON_EXPORT void setArchitecture(triton::arch::architecture_e arch)
Sets the instruction's architecture.
TRITON_EXPORT triton::uint64 getAddress(void) const
Returns the address of the instruction.
TRITON_EXPORT void setBranch(bool flag)
Sets flag to define this instruction as branch or not.
TRITON_EXPORT void setSize(triton::uint32 size)
Sets the size of the instruction.
std::vector< triton::arch::OperandWrapper > operands
A list of operands.
TRITON_EXPORT void setControlFlow(bool flag)
Sets flag to define this instruction changes the control flow or not.
This class is used to represent a memory access.
TRITON_EXPORT void setDisplacement(const triton::arch::Immediate &displacement)
LEA - Sets the displacement operand.
TRITON_EXPORT triton::uint64 getAddress(void) const
Returns the address of the memory.
TRITON_EXPORT triton::uint32 getSize(void) const
Returns the size (in bytes) of the memory vector.
TRITON_EXPORT void setBaseRegister(const triton::arch::Register &base)
LEA - Sets the base register operand.
This class is used as operand wrapper.
This class is used when an instruction has a register operand.
Definition register.hpp:44
TRITON_EXPORT triton::arch::register_e getParent(void) const
Returns the parent id of the register.
Definition register.cpp:58
TRITON_EXPORT triton::arch::register_e getId(void) const
Returns the id of the register.
Definition register.cpp:53
TRITON_EXPORT triton::uint32 getSize(void) const
Returns the size (in bytes) of the register.
Definition register.cpp:68
This class is used to describe the RV32 spec.
triton::uint8 f25[triton::size::qword]
Concrete value of f25.
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
triton::uint8 sp[triton::size::dword]
Concrete value of sp.
triton::uint8 x14[triton::size::dword]
Concrete value of x14.
triton::uint8 x20[triton::size::dword]
Concrete value of x20.
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
triton::uint8 x0[triton::size::dword]
Concrete value of x0.
triton::uint8 x12[triton::size::dword]
Concrete value of x12.
triton::uint8 x31[triton::size::dword]
Concrete value of x31.
triton::uint8 x15[triton::size::dword]
Concrete value of x15.
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
triton::uint8 x10[triton::size::dword]
Concrete value of x10.
triton::uint8 f11[triton::size::qword]
Concrete value of f11.
triton::uint8 x13[triton::size::dword]
Concrete value of x13.
triton::uint8 f0[triton::size::qword]
Concrete value of f0.
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register &reg, bool execCallbacks=true) const
Returns the concrete value of a register.
triton::uint8 x26[triton::size::dword]
Concrete value of x26.
triton::uint8 x22[triton::size::dword]
Concrete value of x22.
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
triton::uint8 f6[triton::size::qword]
Concrete value of f6.
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
triton::uint8 f20[triton::size::qword]
Concrete value of f20.
triton::uint8 f23[triton::size::qword]
Concrete value of f23.
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
triton::uint8 x19[triton::size::dword]
Concrete value of x19.
triton::uint8 f12[triton::size::qword]
Concrete value of f12.
triton::uint8 f3[triton::size::qword]
Concrete value of f3.
triton::uint8 x6[triton::size::dword]
Concrete value of x6.
TRITON_EXPORT riscv32Cpu & operator=(const riscv32Cpu &other)
Copies a riscv32Cpu class.
triton::uint8 x29[triton::size::dword]
Concrete value of x29.
triton::uint8 f2[triton::size::qword]
Concrete value of f2.
triton::uint8 x25[triton::size::dword]
Concrete value of x25.
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
triton::uint8 pc[triton::size::dword]
Concrete value of pc.
triton::uint8 x24[triton::size::dword]
Concrete value of x24.
triton::uint8 f17[triton::size::qword]
Concrete value of f17.
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
triton::uint8 x9[triton::size::dword]
Concrete value of x9.
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
triton::uint8 f24[triton::size::qword]
Concrete value of f24.
triton::uint8 f26[triton::size::qword]
Concrete value of f26.
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
triton::uint8 x18[triton::size::dword]
Concrete value of x18.
triton::uint8 x7[triton::size::dword]
Concrete value of x7.
triton::uint8 f21[triton::size::qword]
Concrete value of f21.
triton::uint8 x5[triton::size::dword]
Concrete value of x5.
triton::uint8 x4[triton::size::dword]
Concrete value of x4.
triton::uint8 x21[triton::size::dword]
Concrete value of x21.
triton::uint8 x8[triton::size::dword]
Concrete value of x8.
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
triton::uint8 f4[triton::size::qword]
Concrete value of f4.
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const
Returns true if regId is a FPU register.
triton::uint8 f22[triton::size::qword]
Concrete value of f22.
triton::uint8 f16[triton::size::qword]
Concrete value of f16.
triton::uint8 f10[triton::size::qword]
Concrete value of f10.
triton::uint8 f29[triton::size::qword]
Concrete value of f29.
triton::uint8 x11[triton::size::dword]
Concrete value of x11.
triton::uint8 f15[triton::size::qword]
Concrete value of f15.
triton::uint8 x23[triton::size::dword]
Concrete value of x23.
triton::uint8 x27[triton::size::dword]
Concrete value of x27.
triton::uint8 f31[triton::size::qword]
Concrete value of f31.
virtual TRITON_EXPORT ~riscv32Cpu()
Destructor.
triton::uint8 f18[triton::size::qword]
Concrete value of f18.
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
TRITON_EXPORT riscv32Cpu(triton::callbacks::Callbacks *callbacks=nullptr)
Constructor.
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register &reg) const
Returns parent register from a given one.
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
triton::uint8 x30[triton::size::dword]
Concrete value of x30.
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
triton::uint8 x1[triton::size::dword]
Concrete value of x1.
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
triton::uint8 x17[triton::size::dword]
Concrete value of x17.
triton::uint8 f5[triton::size::qword]
Concrete value of f5.
triton::uint8 x3[triton::size::dword]
Concrete value of x3.
triton::uint8 f13[triton::size::qword]
Concrete value of f13.
triton::uint8 f28[triton::size::qword]
Concrete value of f28.
triton::uint8 f1[triton::size::qword]
Concrete value of f1.
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
triton::uint8 f9[triton::size::qword]
Concrete value of f9.
triton::uint8 f14[triton::size::qword]
Concrete value of f14.
triton::uint8 x16[triton::size::dword]
Concrete value of x16.
triton::uint8 x28[triton::size::dword]
Concrete value of x28.
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
triton::uint8 f8[triton::size::qword]
Concrete value of f8.
triton::uint8 f19[triton::size::qword]
Concrete value of f19.
triton::uint8 f27[triton::size::qword]
Concrete value of f27.
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
triton::uint8 f7[triton::size::qword]
Concrete value of f7.
triton::uint8 f30[triton::size::qword]
Concrete value of f30.
The riscvSpecifications class defines specifications about the RV32 and RV64 CPU.
TRITON_EXPORT triton::uint32 capstoneInstructionToTritonInstruction(triton::uint32 id) const
Converts a capstone's instruction id to a triton's instruction id.
std::unordered_map< triton::arch::register_e, const triton::arch::Register > id2reg
List of registers specification available for this architecture.
TRITON_EXPORT triton::uint32 getMemoryOperandSpecialSize(triton::uint32 id) const
Returns memory access size if it is specified by instruction.
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister32(triton::uint32 id) const
Converts a capstone's register id to a triton's register id for RV32.
The callbacks class.
Definition callbacks.hpp:79
TRITON_EXPORT triton::ast::SharedAbstractNode processCallbacks(triton::callbacks::callback_e kind, triton::ast::SharedAbstractNode node)
Processes callbacks according to the kind and the C++ polymorphism.
The exception class used by all CPUs.
The exception class used by the disassembler.
The exception class used by register operands.
register_e
Types of register.
Definition archEnums.hpp:68
@ ID_REG_LAST_ITEM
must be the last item
constexpr triton::uint32 byte
byte size in bit
Definition cpuSize.hpp:60
constexpr triton::uint32 dword
dword size in bit
Definition cpuSize.hpp:64
constexpr triton::uint32 dword
dword size in byte
Definition cpuSize.hpp:34
constexpr triton::uint32 dqqword
dqqword size in byte
Definition cpuSize.hpp:44
constexpr triton::uint32 byte
byte size in byte
Definition cpuSize.hpp:30
std::int32_t sint32
signed 32-bits
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits
The Triton namespace.