This class is used to describe the RV64 spec. More...

#include <riscv64Cpu.hpp>

Inheritance diagram for triton::arch::riscv::riscv64Cpu:

Public Member Functions
TRITON_EXPORT	riscv64Cpu (triton::callbacks::Callbacks *callbacks=nullptr)
	Constructor.

TRITON_EXPORT	riscv64Cpu (const riscv64Cpu &other)
	Constructor.

virtual TRITON_EXPORT	~riscv64Cpu ()
	Destructor.

TRITON_EXPORT riscv64Cpu &	operator= (const riscv64Cpu &other)
	Copies a riscv64Cpu class.

TRITON_EXPORT bool	isGPR (triton::arch::register_e regId) const
	Returns true if regId is a GRP.

TRITON_EXPORT bool	isFPU (triton::arch::register_e regId) const
	Returns true if regId is a FPU register.

TRITON_EXPORT bool	isFlag (triton::arch::register_e regId) const
	Returns true if the register ID is a flag.

TRITON_EXPORT bool	isRegister (triton::arch::register_e regId) const
	Returns true if the register ID is a register.

TRITON_EXPORT bool	isRegisterValid (triton::arch::register_e regId) const
	Returns true if the register ID is valid.

TRITON_EXPORT bool	isThumb (void) const
	Returns true if the execution mode is Thumb. Only useful for Arm32.

TRITON_EXPORT bool	isMemoryExclusive (const triton::arch::MemoryAccess &mem) const
	Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.

TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > &	getAllRegisters (void) const
	Returns all registers.

TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > &	getConcreteMemory (void) const
	Return all memory.

TRITON_EXPORT const triton::arch::Register &	getParentRegister (const triton::arch::Register &reg) const
	Returns parent register from a given one.

TRITON_EXPORT const triton::arch::Register &	getParentRegister (triton::arch::register_e id) const
	Returns parent register from a given one.

TRITON_EXPORT const triton::arch::Register &	getProgramCounter (void) const
	Returns the program counter register.

TRITON_EXPORT const triton::arch::Register &	getRegister (triton::arch::register_e id) const
	Returns register from id.

TRITON_EXPORT const triton::arch::Register &	getRegister (const std::string &name) const
	Returns register from name.

TRITON_EXPORT const triton::arch::Register &	getStackPointer (void) const
	Returns the stack pointer register.

TRITON_EXPORT std::set< const triton::arch::Register * >	getParentRegisters (void) const
	Returns all parent registers.

TRITON_EXPORT std::vector< triton::uint8 >	getConcreteMemoryAreaValue (triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
	Returns the concrete value of a memory area.

TRITON_EXPORT triton::arch::endianness_e	getEndianness (void) const
	Returns the kind of endianness as triton::arch::endianness_e.

TRITON_EXPORT triton::uint32	numberOfRegisters (void) const
	Returns the number of registers according to the CPU architecture.

TRITON_EXPORT triton::uint32	gprBitSize (void) const
	Returns the bit in bit of the General Purpose Registers.

TRITON_EXPORT triton::uint32	gprSize (void) const
	Returns the bit in byte of the General Purpose Registers.

TRITON_EXPORT triton::uint512	getConcreteMemoryValue (const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
	Returns the concrete value of memory cells.

TRITON_EXPORT triton::uint512	getConcreteRegisterValue (const triton::arch::Register &reg, bool execCallbacks=true) const
	Returns the concrete value of a register.

TRITON_EXPORT triton::uint8	getConcreteMemoryValue (triton::uint64 addr, bool execCallbacks=true) const
	Returns the concrete value of a memory cell.

TRITON_EXPORT void	clear (void)
	Clears the architecture states (registers and memory).

TRITON_EXPORT void	disassembly (triton::arch::Instruction &inst)
	Disassembles the instruction according to the architecture.

TRITON_EXPORT void	setConcreteMemoryAreaValue (triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
	[architecture api] - Sets the concrete value of a memory area.

TRITON_EXPORT void	setConcreteMemoryAreaValue (triton::uint64 baseAddr, const void *area, triton::usize size, bool execCallbacks=true)
	[architecture api] - Sets the concrete value of a memory area.

TRITON_EXPORT void	setConcreteMemoryValue (const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
	[architecture api] - Sets the concrete value of memory cells.

TRITON_EXPORT void	setConcreteMemoryValue (triton::uint64 addr, triton::uint8 value, bool execCallbacks=true)
	[architecture api] - Sets the concrete value of a memory cell.

TRITON_EXPORT void	setConcreteRegisterValue (const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
	[architecture api] - Sets the concrete value of a register.

TRITON_EXPORT void	setThumb (bool state)
	Sets CPU state to Thumb mode.

TRITON_EXPORT void	setMemoryExclusiveTag (const triton::arch::MemoryAccess &mem, bool tag)
	Sets exclusive memory access tag. Only valid for Arm32 and AArch64.

TRITON_EXPORT bool	isConcreteMemoryValueDefined (const triton::arch::MemoryAccess &mem) const
	Returns true if memory cells have a defined concrete value.

TRITON_EXPORT bool	isConcreteMemoryValueDefined (triton::uint64 baseAddr, triton::usize size=1) const
	Returns true if memory cells have a defined concrete value.

TRITON_EXPORT void	clearConcreteMemoryValue (const triton::arch::MemoryAccess &mem)
	Clears concrete values assigned to the memory cells.

TRITON_EXPORT void	clearConcreteMemoryValue (triton::uint64 baseAddr, triton::usize size=1)
	Clears concrete values assigned to the memory cells.

Public Member Functions inherited from triton::arch::CpuInterface
virtual TRITON_EXPORT	~CpuInterface ()
	Destructor.

Public Member Functions inherited from triton::arch::riscv::riscvSpecifications
TRITON_EXPORT	riscvSpecifications (triton::arch::architecture_e)
	Constructor.

TRITON_EXPORT triton::arch::register_e	capstoneRegisterToTritonRegister64 (triton::uint32 id) const
	Converts a capstone's register id to a triton's register id for RV64.

TRITON_EXPORT triton::arch::register_e	capstoneRegisterToTritonRegister32 (triton::uint32 id) const
	Converts a capstone's register id to a triton's register id for RV32.

TRITON_EXPORT triton::uint32	capstoneInstructionToTritonInstruction (triton::uint32 id) const
	Converts a capstone's instruction id to a triton's instruction id.

TRITON_EXPORT triton::arch::riscv::insn_group_e	capstoneGroupToTritonGroup (triton::uint32 id) const
	Converts a capstone's group id to a triton's group id.

TRITON_EXPORT triton::uint32	getMemoryOperandSpecialSize (triton::uint32 id) const
	Returns memory access size if it is specified by instruction.

Protected Attributes
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > >	memory
	map of address -> concrete value

triton::uint8	x0 [triton::size::qword]
	Concrete value of x0.

triton::uint8	x1 [triton::size::qword]
	Concrete value of x1.

triton::uint8	sp [triton::size::qword]
	Concrete value of sp.

triton::uint8	x3 [triton::size::qword]
	Concrete value of x3.

triton::uint8	x4 [triton::size::qword]
	Concrete value of x4.

triton::uint8	x5 [triton::size::qword]
	Concrete value of x5.

triton::uint8	x6 [triton::size::qword]
	Concrete value of x6.

triton::uint8	x7 [triton::size::qword]
	Concrete value of x7.

triton::uint8	x8 [triton::size::qword]
	Concrete value of x8.

triton::uint8	x9 [triton::size::qword]
	Concrete value of x9.

triton::uint8	x10 [triton::size::qword]
	Concrete value of x10.

triton::uint8	x11 [triton::size::qword]
	Concrete value of x11.

triton::uint8	x12 [triton::size::qword]
	Concrete value of x12.

triton::uint8	x13 [triton::size::qword]
	Concrete value of x13.

triton::uint8	x14 [triton::size::qword]
	Concrete value of x14.

triton::uint8	x15 [triton::size::qword]
	Concrete value of x15.

triton::uint8	x16 [triton::size::qword]
	Concrete value of x16.

triton::uint8	x17 [triton::size::qword]
	Concrete value of x17.

triton::uint8	x18 [triton::size::qword]
	Concrete value of x18.

triton::uint8	x19 [triton::size::qword]
	Concrete value of x19.

triton::uint8	x20 [triton::size::qword]
	Concrete value of x20.

triton::uint8	x21 [triton::size::qword]
	Concrete value of x21.

triton::uint8	x22 [triton::size::qword]
	Concrete value of x22.

triton::uint8	x23 [triton::size::qword]
	Concrete value of x23.

triton::uint8	x24 [triton::size::qword]
	Concrete value of x24.

triton::uint8	x25 [triton::size::qword]
	Concrete value of x25.

triton::uint8	x26 [triton::size::qword]
	Concrete value of x26.

triton::uint8	x27 [triton::size::qword]
	Concrete value of x27.

triton::uint8	x28 [triton::size::qword]
	Concrete value of x28.

triton::uint8	x29 [triton::size::qword]
	Concrete value of x29.

triton::uint8	x30 [triton::size::qword]
	Concrete value of x30.

triton::uint8	x31 [triton::size::qword]
	Concrete value of x31.

triton::uint8	f0 [triton::size::dqword]
	Concrete value of f0.

triton::uint8	f1 [triton::size::dqword]
	Concrete value of f1.

triton::uint8	f2 [triton::size::dqword]
	Concrete value of f2.

triton::uint8	f3 [triton::size::dqword]
	Concrete value of f3.

triton::uint8	f4 [triton::size::dqword]
	Concrete value of f4.

triton::uint8	f5 [triton::size::dqword]
	Concrete value of f5.

triton::uint8	f6 [triton::size::dqword]
	Concrete value of f6.

triton::uint8	f7 [triton::size::dqword]
	Concrete value of f7.

triton::uint8	f8 [triton::size::dqword]
	Concrete value of f8.

triton::uint8	f9 [triton::size::dqword]
	Concrete value of f9.

triton::uint8	f10 [triton::size::dqword]
	Concrete value of f10.

triton::uint8	f11 [triton::size::dqword]
	Concrete value of f11.

triton::uint8	f12 [triton::size::dqword]
	Concrete value of f12.

triton::uint8	f13 [triton::size::dqword]
	Concrete value of f13.

triton::uint8	f14 [triton::size::dqword]
	Concrete value of f14.

triton::uint8	f15 [triton::size::dqword]
	Concrete value of f15.

triton::uint8	f16 [triton::size::dqword]
	Concrete value of f16.

triton::uint8	f17 [triton::size::dqword]
	Concrete value of f17.

triton::uint8	f18 [triton::size::dqword]
	Concrete value of f18.

triton::uint8	f19 [triton::size::dqword]
	Concrete value of f19.

triton::uint8	f20 [triton::size::dqword]
	Concrete value of f20.

triton::uint8	f21 [triton::size::dqword]
	Concrete value of f21.

triton::uint8	f22 [triton::size::dqword]
	Concrete value of f22.

triton::uint8	f23 [triton::size::dqword]
	Concrete value of f23.

triton::uint8	f24 [triton::size::dqword]
	Concrete value of f24.

triton::uint8	f25 [triton::size::dqword]
	Concrete value of f25.

triton::uint8	f26 [triton::size::dqword]
	Concrete value of f26.

triton::uint8	f27 [triton::size::dqword]
	Concrete value of f27.

triton::uint8	f28 [triton::size::dqword]
	Concrete value of f28.

triton::uint8	f29 [triton::size::dqword]
	Concrete value of f29.

triton::uint8	f30 [triton::size::dqword]
	Concrete value of f30.

triton::uint8	f31 [triton::size::dqword]
	Concrete value of f31.

triton::uint8	pc [triton::size::qword]
	Concrete value of pc.

Protected Attributes inherited from triton::arch::riscv::riscvSpecifications
std::unordered_map< triton::arch::register_e, const triton::arch::Register >	id2reg
	List of registers specification available for this architecture.

std::unordered_map< std::string, triton::arch::register_e >	name2id

Detailed Description

This class is used to describe the RV64 spec.

Definition at line 53 of file riscv64Cpu.hpp.

Constructor & Destructor Documentation

◆ riscv64Cpu() [1/2]

triton::arch::riscv::riscv64Cpu::riscv64Cpu ( triton::callbacks::Callbacks * callbacks = nullptr )

Constructor.

Definition at line 26 of file riscv64Cpu.cpp.

◆ riscv64Cpu() [2/2]

triton::arch::riscv::riscv64Cpu::riscv64Cpu ( const riscv64Cpu & other )

Constructor.

Definition at line 35 of file riscv64Cpu.cpp.

◆ ~riscv64Cpu()

triton::arch::riscv::riscv64Cpu::~riscv64Cpu ( )

virtual

Destructor.

Definition at line 40 of file riscv64Cpu.cpp.

Member Function Documentation

◆ clear()

void triton::arch::riscv::riscv64Cpu::clear ( void )

virtual

Clears the architecture states (registers and memory).

Implements triton::arch::CpuInterface.

Definition at line 133 of file riscv64Cpu.cpp.

◆ clearConcreteMemoryValue() [1/2]

void triton::arch::riscv::riscv64Cpu::clearConcreteMemoryValue ( const triton::arch::MemoryAccess & mem )

virtual

Clears concrete values assigned to the memory cells.

Implements triton::arch::CpuInterface.

Definition at line 726 of file riscv64Cpu.cpp.

◆ clearConcreteMemoryValue() [2/2]

void triton::arch::riscv::riscv64Cpu::clearConcreteMemoryValue	(	triton::uint64	baseAddr,
		triton::usize	size = 1 )

virtual

Clears concrete values assigned to the memory cells.

Implements triton::arch::CpuInterface.

Definition at line 731 of file riscv64Cpu.cpp.

◆ disassembly()

void triton::arch::riscv::riscv64Cpu::disassembly ( triton::arch::Instruction & inst )

virtual

Disassembles the instruction according to the architecture.

Implements triton::arch::CpuInterface.

Definition at line 324 of file riscv64Cpu.cpp.

◆ getAllRegisters()

const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & triton::arch::riscv::riscv64Cpu::getAllRegisters ( void ) const

virtual

Returns all registers.

Implements triton::arch::CpuInterface.

Definition at line 257 of file riscv64Cpu.cpp.

◆ getConcreteMemory()

const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & triton::arch::riscv::riscv64Cpu::getConcreteMemory ( void ) const

virtual

Return all memory.

Implements triton::arch::CpuInterface.

Definition at line 261 of file riscv64Cpu.cpp.

◆ getConcreteMemoryAreaValue()

std::vector< triton::uint8 > triton::arch::riscv::riscv64Cpu::getConcreteMemoryAreaValue	(	triton::uint64	baseAddr,
		triton::usize	size,
		bool	execCallbacks = true ) const

virtual

Returns the concrete value of a memory area.

Implements triton::arch::CpuInterface.

Definition at line 471 of file riscv64Cpu.cpp.

◆ getConcreteMemoryValue() [1/2]

triton::uint512 triton::arch::riscv::riscv64Cpu::getConcreteMemoryValue	(	const triton::arch::MemoryAccess &	mem,
		bool	execCallbacks = true ) const

virtual

Returns the concrete value of memory cells.

Implements triton::arch::CpuInterface.

Definition at line 450 of file riscv64Cpu.cpp.

◆ getConcreteMemoryValue() [2/2]

triton::uint8 triton::arch::riscv::riscv64Cpu::getConcreteMemoryValue	(	triton::uint64	addr,
		bool	execCallbacks = true ) const

virtual

Returns the concrete value of a memory cell.

Implements triton::arch::CpuInterface.

Definition at line 437 of file riscv64Cpu.cpp.

◆ getConcreteRegisterValue()

triton::uint512 triton::arch::riscv::riscv64Cpu::getConcreteRegisterValue	(	const triton::arch::Register &	reg,
		bool	execCallbacks = true ) const

virtual

Returns the concrete value of a register.

Implements triton::arch::CpuInterface.

Definition at line 481 of file riscv64Cpu.cpp.

◆ getEndianness()

triton::arch::endianness_e triton::arch::riscv::riscv64Cpu::getEndianness ( void ) const

virtual

Returns the kind of endianness as triton::arch::endianness_e.

Implements triton::arch::CpuInterface.

Definition at line 212 of file riscv64Cpu.cpp.

◆ getParentRegister() [1/2]

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getParentRegister ( const triton::arch::Register & reg ) const

virtual

Returns parent register from a given one.

Implements triton::arch::CpuInterface.

Definition at line 305 of file riscv64Cpu.cpp.

◆ getParentRegister() [2/2]

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getParentRegister ( triton::arch::register_e id ) const

virtual

Returns parent register from a given one.

Implements triton::arch::CpuInterface.

Definition at line 310 of file riscv64Cpu.cpp.

◆ getParentRegisters()

std::set< const triton::arch::Register * > triton::arch::riscv::riscv64Cpu::getParentRegisters ( void ) const

virtual

Returns all parent registers.

Implements triton::arch::CpuInterface.

Definition at line 265 of file riscv64Cpu.cpp.

◆ getProgramCounter()

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getProgramCounter ( void ) const

virtual

Returns the program counter register.

Implements triton::arch::CpuInterface.

Definition at line 315 of file riscv64Cpu.cpp.

◆ getRegister() [1/2]

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getRegister ( const std::string & name ) const

virtual

Returns register from name.

Implements triton::arch::CpuInterface.

Definition at line 294 of file riscv64Cpu.cpp.

◆ getRegister() [2/2]

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getRegister ( triton::arch::register_e id ) const

virtual

Returns register from id.

Implements triton::arch::CpuInterface.

Definition at line 285 of file riscv64Cpu.cpp.

◆ getStackPointer()

const triton::arch::Register & triton::arch::riscv::riscv64Cpu::getStackPointer ( void ) const

virtual

Returns the stack pointer register.

Implements triton::arch::CpuInterface.

Definition at line 320 of file riscv64Cpu.cpp.

◆ gprBitSize()

triton::uint32 triton::arch::riscv::riscv64Cpu::gprBitSize ( void ) const

virtual

Returns the bit in bit of the General Purpose Registers.

Implements triton::arch::CpuInterface.

Definition at line 252 of file riscv64Cpu.cpp.

◆ gprSize()

triton::uint32 triton::arch::riscv::riscv64Cpu::gprSize ( void ) const

virtual

Returns the bit in byte of the General Purpose Registers.

Implements triton::arch::CpuInterface.

Definition at line 247 of file riscv64Cpu.cpp.

◆ isConcreteMemoryValueDefined() [1/2]

bool triton::arch::riscv::riscv64Cpu::isConcreteMemoryValueDefined ( const triton::arch::MemoryAccess & mem ) const

virtual

Returns true if memory cells have a defined concrete value.

Implements triton::arch::CpuInterface.

Definition at line 711 of file riscv64Cpu.cpp.

◆ isConcreteMemoryValueDefined() [2/2]

bool triton::arch::riscv::riscv64Cpu::isConcreteMemoryValueDefined	(	triton::uint64	baseAddr,
		triton::usize	size = 1 ) const

virtual

Returns true if memory cells have a defined concrete value.

Implements triton::arch::CpuInterface.

Definition at line 716 of file riscv64Cpu.cpp.

◆ isFlag()

bool triton::arch::riscv::riscv64Cpu::isFlag ( triton::arch::register_e regId ) const

virtual

Returns true if the register ID is a flag.

Implements triton::arch::CpuInterface.

Definition at line 237 of file riscv64Cpu.cpp.

◆ isFPU()

bool triton::arch::riscv::riscv64Cpu::isFPU ( triton::arch::register_e regId ) const

Returns true if regId is a FPU register.

Definition at line 232 of file riscv64Cpu.cpp.

◆ isGPR()

bool triton::arch::riscv::riscv64Cpu::isGPR ( triton::arch::register_e regId ) const

Returns true if regId is a GRP.

Definition at line 227 of file riscv64Cpu.cpp.

◆ isMemoryExclusive()

bool triton::arch::riscv::riscv64Cpu::isMemoryExclusive ( const triton::arch::MemoryAccess & mem ) const

virtual

Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.

Implements triton::arch::CpuInterface.

Definition at line 700 of file riscv64Cpu.cpp.

◆ isRegister()

bool triton::arch::riscv::riscv64Cpu::isRegister ( triton::arch::register_e regId ) const

virtual

Returns true if the register ID is a register.

Implements triton::arch::CpuInterface.

Definition at line 217 of file riscv64Cpu.cpp.

◆ isRegisterValid()

bool triton::arch::riscv::riscv64Cpu::isRegisterValid ( triton::arch::register_e regId ) const

virtual

Returns true if the register ID is valid.

Implements triton::arch::CpuInterface.

Definition at line 222 of file riscv64Cpu.cpp.

◆ isThumb()

bool triton::arch::riscv::riscv64Cpu::isThumb ( void ) const

virtual

Returns true if the execution mode is Thumb. Only useful for Arm32.

Implements triton::arch::CpuInterface.

Definition at line 689 of file riscv64Cpu.cpp.

◆ numberOfRegisters()

triton::uint32 triton::arch::riscv::riscv64Cpu::numberOfRegisters ( void ) const

virtual

Returns the number of registers according to the CPU architecture.

Implements triton::arch::CpuInterface.

Definition at line 242 of file riscv64Cpu.cpp.

◆ operator=()

riscv64Cpu & triton::arch::riscv::riscv64Cpu::operator= ( const riscv64Cpu & other )

Copies a riscv64Cpu class.

Definition at line 206 of file riscv64Cpu.cpp.

◆ setConcreteMemoryAreaValue() [1/2]

void triton::arch::riscv::riscv64Cpu::setConcreteMemoryAreaValue	(	triton::uint64	baseAddr,
		const std::vector< triton::uint8 > &	values,
		bool	execCallbacks = true )

virtual

[architecture api] - Sets the concrete value of a memory area.

Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.

Implements triton::arch::CpuInterface.

Definition at line 589 of file riscv64Cpu.cpp.

◆ setConcreteMemoryAreaValue() [2/2]

void triton::arch::riscv::riscv64Cpu::setConcreteMemoryAreaValue	(	triton::uint64	baseAddr,
		const void *	area,
		triton::usize	size,
		bool	execCallbacks = true )

virtual

[architecture api] - Sets the concrete value of a memory area.

Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.

Implements triton::arch::CpuInterface.

Definition at line 598 of file riscv64Cpu.cpp.

◆ setConcreteMemoryValue() [1/2]

void triton::arch::riscv::riscv64Cpu::setConcreteMemoryValue	(	const triton::arch::MemoryAccess &	mem,
		const triton::uint512 &	value,
		bool	execCallbacks = true )

virtual

[architecture api] - Sets the concrete value of memory cells.

Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.

Implements triton::arch::CpuInterface.

Definition at line 568 of file riscv64Cpu.cpp.

◆ setConcreteMemoryValue() [2/2]

void triton::arch::riscv::riscv64Cpu::setConcreteMemoryValue	(	triton::uint64	addr,
		triton::uint8	value,
		bool	execCallbacks = true )

virtual

[architecture api] - Sets the concrete value of a memory cell.

Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.

Implements triton::arch::CpuInterface.

Definition at line 561 of file riscv64Cpu.cpp.

◆ setConcreteRegisterValue()

void triton::arch::riscv::riscv64Cpu::setConcreteRegisterValue	(	const triton::arch::Register &	reg,
		const triton::uint512 &	value,
		bool	execCallbacks = true )

virtual

[architecture api] - Sets the concrete value of a register.

Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.

Implements triton::arch::CpuInterface.

Definition at line 607 of file riscv64Cpu.cpp.

◆ setMemoryExclusiveTag()

void triton::arch::riscv::riscv64Cpu::setMemoryExclusiveTag	(	const triton::arch::MemoryAccess &	mem,
		bool	tag )

virtual

Sets exclusive memory access tag. Only valid for Arm32 and AArch64.

Implements triton::arch::CpuInterface.

Definition at line 706 of file riscv64Cpu.cpp.

◆ setThumb()

void triton::arch::riscv::riscv64Cpu::setThumb ( bool state )

virtual

Sets CPU state to Thumb mode.

Implements triton::arch::CpuInterface.

Definition at line 695 of file riscv64Cpu.cpp.

Member Data Documentation

◆ f0

triton::uint8 triton::arch::riscv::riscv64Cpu::f0[triton::size::dqword]

protected

Concrete value of f0.

Definition at line 146 of file riscv64Cpu.hpp.

◆ f1

triton::uint8 triton::arch::riscv::riscv64Cpu::f1[triton::size::dqword]

protected

Concrete value of f1.

Definition at line 148 of file riscv64Cpu.hpp.

◆ f10

triton::uint8 triton::arch::riscv::riscv64Cpu::f10[triton::size::dqword]

protected

Concrete value of f10.

Definition at line 166 of file riscv64Cpu.hpp.

◆ f11

triton::uint8 triton::arch::riscv::riscv64Cpu::f11[triton::size::dqword]

protected

Concrete value of f11.

Definition at line 168 of file riscv64Cpu.hpp.

◆ f12

triton::uint8 triton::arch::riscv::riscv64Cpu::f12[triton::size::dqword]

protected

Concrete value of f12.

Definition at line 170 of file riscv64Cpu.hpp.

◆ f13

triton::uint8 triton::arch::riscv::riscv64Cpu::f13[triton::size::dqword]

protected

Concrete value of f13.

Definition at line 172 of file riscv64Cpu.hpp.

◆ f14

triton::uint8 triton::arch::riscv::riscv64Cpu::f14[triton::size::dqword]

protected

Concrete value of f14.

Definition at line 174 of file riscv64Cpu.hpp.

◆ f15

triton::uint8 triton::arch::riscv::riscv64Cpu::f15[triton::size::dqword]

protected

Concrete value of f15.

Definition at line 176 of file riscv64Cpu.hpp.

◆ f16

triton::uint8 triton::arch::riscv::riscv64Cpu::f16[triton::size::dqword]

protected

Concrete value of f16.

Definition at line 178 of file riscv64Cpu.hpp.

◆ f17

triton::uint8 triton::arch::riscv::riscv64Cpu::f17[triton::size::dqword]

protected

Concrete value of f17.

Definition at line 180 of file riscv64Cpu.hpp.

◆ f18

triton::uint8 triton::arch::riscv::riscv64Cpu::f18[triton::size::dqword]

protected

Concrete value of f18.

Definition at line 182 of file riscv64Cpu.hpp.

◆ f19

triton::uint8 triton::arch::riscv::riscv64Cpu::f19[triton::size::dqword]

protected

Concrete value of f19.

Definition at line 184 of file riscv64Cpu.hpp.

◆ f2

triton::uint8 triton::arch::riscv::riscv64Cpu::f2[triton::size::dqword]

protected

Concrete value of f2.

Definition at line 150 of file riscv64Cpu.hpp.

◆ f20

triton::uint8 triton::arch::riscv::riscv64Cpu::f20[triton::size::dqword]

protected

Concrete value of f20.

Definition at line 186 of file riscv64Cpu.hpp.

◆ f21

triton::uint8 triton::arch::riscv::riscv64Cpu::f21[triton::size::dqword]

protected

Concrete value of f21.

Definition at line 188 of file riscv64Cpu.hpp.

◆ f22

triton::uint8 triton::arch::riscv::riscv64Cpu::f22[triton::size::dqword]

protected

Concrete value of f22.

Definition at line 190 of file riscv64Cpu.hpp.

◆ f23

triton::uint8 triton::arch::riscv::riscv64Cpu::f23[triton::size::dqword]

protected

Concrete value of f23.

Definition at line 192 of file riscv64Cpu.hpp.

◆ f24

triton::uint8 triton::arch::riscv::riscv64Cpu::f24[triton::size::dqword]

protected

Concrete value of f24.

Definition at line 194 of file riscv64Cpu.hpp.

◆ f25

triton::uint8 triton::arch::riscv::riscv64Cpu::f25[triton::size::dqword]

protected

Concrete value of f25.

Definition at line 196 of file riscv64Cpu.hpp.

◆ f26

triton::uint8 triton::arch::riscv::riscv64Cpu::f26[triton::size::dqword]

protected

Concrete value of f26.

Definition at line 198 of file riscv64Cpu.hpp.

◆ f27

triton::uint8 triton::arch::riscv::riscv64Cpu::f27[triton::size::dqword]

protected

Concrete value of f27.

Definition at line 200 of file riscv64Cpu.hpp.

◆ f28

triton::uint8 triton::arch::riscv::riscv64Cpu::f28[triton::size::dqword]

protected

Concrete value of f28.

Definition at line 202 of file riscv64Cpu.hpp.

◆ f29

triton::uint8 triton::arch::riscv::riscv64Cpu::f29[triton::size::dqword]

protected

Concrete value of f29.

Definition at line 204 of file riscv64Cpu.hpp.

◆ f3

triton::uint8 triton::arch::riscv::riscv64Cpu::f3[triton::size::dqword]

protected

Concrete value of f3.

Definition at line 152 of file riscv64Cpu.hpp.

◆ f30

triton::uint8 triton::arch::riscv::riscv64Cpu::f30[triton::size::dqword]

protected

Concrete value of f30.

Definition at line 206 of file riscv64Cpu.hpp.

◆ f31

triton::uint8 triton::arch::riscv::riscv64Cpu::f31[triton::size::dqword]

protected

Concrete value of f31.

Definition at line 208 of file riscv64Cpu.hpp.

◆ f4

triton::uint8 triton::arch::riscv::riscv64Cpu::f4[triton::size::dqword]

protected

Concrete value of f4.

Definition at line 154 of file riscv64Cpu.hpp.

◆ f5

triton::uint8 triton::arch::riscv::riscv64Cpu::f5[triton::size::dqword]

protected

Concrete value of f5.

Definition at line 156 of file riscv64Cpu.hpp.

◆ f6

triton::uint8 triton::arch::riscv::riscv64Cpu::f6[triton::size::dqword]

protected

Concrete value of f6.

Definition at line 158 of file riscv64Cpu.hpp.

◆ f7

triton::uint8 triton::arch::riscv::riscv64Cpu::f7[triton::size::dqword]

protected

Concrete value of f7.

Definition at line 160 of file riscv64Cpu.hpp.

◆ f8

triton::uint8 triton::arch::riscv::riscv64Cpu::f8[triton::size::dqword]

protected

Concrete value of f8.

Definition at line 162 of file riscv64Cpu.hpp.

◆ f9

triton::uint8 triton::arch::riscv::riscv64Cpu::f9[triton::size::dqword]

protected

Concrete value of f9.

Definition at line 164 of file riscv64Cpu.hpp.

◆ memory

std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64> > triton::arch::riscv::riscv64Cpu::memory

protected

map of address -> concrete value

item1: memory address
item2: concrete value

Definition at line 79 of file riscv64Cpu.hpp.

◆ pc

triton::uint8 triton::arch::riscv::riscv64Cpu::pc[triton::size::qword]

protected

Concrete value of pc.

Definition at line 210 of file riscv64Cpu.hpp.

◆ sp

triton::uint8 triton::arch::riscv::riscv64Cpu::sp[triton::size::qword]

protected

Concrete value of sp.

Definition at line 86 of file riscv64Cpu.hpp.

◆ x0

triton::uint8 triton::arch::riscv::riscv64Cpu::x0[triton::size::qword]

protected

Concrete value of x0.

Definition at line 82 of file riscv64Cpu.hpp.

◆ x1

triton::uint8 triton::arch::riscv::riscv64Cpu::x1[triton::size::qword]

protected

Concrete value of x1.

Definition at line 84 of file riscv64Cpu.hpp.

◆ x10

triton::uint8 triton::arch::riscv::riscv64Cpu::x10[triton::size::qword]

protected

Concrete value of x10.

Definition at line 102 of file riscv64Cpu.hpp.

◆ x11

triton::uint8 triton::arch::riscv::riscv64Cpu::x11[triton::size::qword]

protected

Concrete value of x11.

Definition at line 104 of file riscv64Cpu.hpp.

◆ x12

triton::uint8 triton::arch::riscv::riscv64Cpu::x12[triton::size::qword]

protected

Concrete value of x12.

Definition at line 106 of file riscv64Cpu.hpp.

◆ x13

triton::uint8 triton::arch::riscv::riscv64Cpu::x13[triton::size::qword]

protected

Concrete value of x13.

Definition at line 108 of file riscv64Cpu.hpp.

◆ x14

triton::uint8 triton::arch::riscv::riscv64Cpu::x14[triton::size::qword]

protected

Concrete value of x14.

Definition at line 110 of file riscv64Cpu.hpp.

◆ x15

triton::uint8 triton::arch::riscv::riscv64Cpu::x15[triton::size::qword]

protected

Concrete value of x15.

Definition at line 112 of file riscv64Cpu.hpp.

◆ x16

triton::uint8 triton::arch::riscv::riscv64Cpu::x16[triton::size::qword]

protected

Concrete value of x16.

Definition at line 114 of file riscv64Cpu.hpp.

◆ x17

triton::uint8 triton::arch::riscv::riscv64Cpu::x17[triton::size::qword]

protected

Concrete value of x17.

Definition at line 116 of file riscv64Cpu.hpp.

◆ x18

triton::uint8 triton::arch::riscv::riscv64Cpu::x18[triton::size::qword]

protected

Concrete value of x18.

Definition at line 118 of file riscv64Cpu.hpp.

◆ x19

triton::uint8 triton::arch::riscv::riscv64Cpu::x19[triton::size::qword]

protected

Concrete value of x19.

Definition at line 120 of file riscv64Cpu.hpp.

◆ x20

triton::uint8 triton::arch::riscv::riscv64Cpu::x20[triton::size::qword]

protected

Concrete value of x20.

Definition at line 122 of file riscv64Cpu.hpp.

◆ x21

triton::uint8 triton::arch::riscv::riscv64Cpu::x21[triton::size::qword]

protected

Concrete value of x21.

Definition at line 124 of file riscv64Cpu.hpp.

◆ x22

triton::uint8 triton::arch::riscv::riscv64Cpu::x22[triton::size::qword]

protected

Concrete value of x22.

Definition at line 126 of file riscv64Cpu.hpp.

◆ x23

triton::uint8 triton::arch::riscv::riscv64Cpu::x23[triton::size::qword]

protected

Concrete value of x23.

Definition at line 128 of file riscv64Cpu.hpp.

◆ x24

triton::uint8 triton::arch::riscv::riscv64Cpu::x24[triton::size::qword]

protected

Concrete value of x24.

Definition at line 130 of file riscv64Cpu.hpp.

◆ x25

triton::uint8 triton::arch::riscv::riscv64Cpu::x25[triton::size::qword]

protected

Concrete value of x25.

Definition at line 132 of file riscv64Cpu.hpp.

◆ x26

triton::uint8 triton::arch::riscv::riscv64Cpu::x26[triton::size::qword]

protected

Concrete value of x26.

Definition at line 134 of file riscv64Cpu.hpp.

◆ x27

triton::uint8 triton::arch::riscv::riscv64Cpu::x27[triton::size::qword]

protected

Concrete value of x27.

Definition at line 136 of file riscv64Cpu.hpp.

◆ x28

triton::uint8 triton::arch::riscv::riscv64Cpu::x28[triton::size::qword]

protected

Concrete value of x28.

Definition at line 138 of file riscv64Cpu.hpp.

◆ x29

triton::uint8 triton::arch::riscv::riscv64Cpu::x29[triton::size::qword]

protected

Concrete value of x29.

Definition at line 140 of file riscv64Cpu.hpp.

◆ x3

triton::uint8 triton::arch::riscv::riscv64Cpu::x3[triton::size::qword]

protected

Concrete value of x3.

Definition at line 88 of file riscv64Cpu.hpp.

◆ x30

triton::uint8 triton::arch::riscv::riscv64Cpu::x30[triton::size::qword]

protected

Concrete value of x30.

Definition at line 142 of file riscv64Cpu.hpp.

◆ x31

triton::uint8 triton::arch::riscv::riscv64Cpu::x31[triton::size::qword]

protected

Concrete value of x31.

Definition at line 144 of file riscv64Cpu.hpp.

◆ x4

triton::uint8 triton::arch::riscv::riscv64Cpu::x4[triton::size::qword]

protected

Concrete value of x4.

Definition at line 90 of file riscv64Cpu.hpp.

◆ x5

triton::uint8 triton::arch::riscv::riscv64Cpu::x5[triton::size::qword]

protected

Concrete value of x5.

Definition at line 92 of file riscv64Cpu.hpp.

◆ x6

triton::uint8 triton::arch::riscv::riscv64Cpu::x6[triton::size::qword]

protected

Concrete value of x6.

Definition at line 94 of file riscv64Cpu.hpp.

◆ x7

triton::uint8 triton::arch::riscv::riscv64Cpu::x7[triton::size::qword]

protected

Concrete value of x7.

Definition at line 96 of file riscv64Cpu.hpp.

◆ x8

triton::uint8 triton::arch::riscv::riscv64Cpu::x8[triton::size::qword]

protected

Concrete value of x8.

Definition at line 98 of file riscv64Cpu.hpp.

◆ x9

triton::uint8 triton::arch::riscv::riscv64Cpu::x9[triton::size::qword]

protected

Concrete value of x9.

Definition at line 100 of file riscv64Cpu.hpp.

The documentation for this class was generated from the following files:

/Users/jonathan/Works/Tools/Triton/src/libtriton/includes/triton/riscv64Cpu.hpp
/Users/jonathan/Works/Tools/Triton/src/libtriton/arch/riscv/riscv64Cpu.cpp

Public Member Functions

Protected Attributes

Detailed Description

Constructor & Destructor Documentation

◆ riscv64Cpu() [1/2]

◆ riscv64Cpu() [2/2]

◆ ~riscv64Cpu()

Member Function Documentation

◆ clear()

◆ clearConcreteMemoryValue() [1/2]

◆ clearConcreteMemoryValue() [2/2]

◆ disassembly()

◆ getAllRegisters()

◆ getConcreteMemory()

◆ getConcreteMemoryAreaValue()

◆ getConcreteMemoryValue() [1/2]

◆ getConcreteMemoryValue() [2/2]

◆ getConcreteRegisterValue()

◆ getEndianness()

◆ getParentRegister() [1/2]

◆ getParentRegister() [2/2]

◆ getParentRegisters()

◆ getProgramCounter()

◆ getRegister() [1/2]

◆ getRegister() [2/2]

◆ getStackPointer()

◆ gprBitSize()

◆ gprSize()

◆ isConcreteMemoryValueDefined() [1/2]

◆ isConcreteMemoryValueDefined() [2/2]

◆ isFlag()

◆ isFPU()

◆ isGPR()

◆ isMemoryExclusive()

◆ isRegister()

◆ isRegisterValid()

◆ isThumb()

◆ numberOfRegisters()

◆ operator=()

◆ setConcreteMemoryAreaValue() [1/2]

◆ setConcreteMemoryAreaValue() [2/2]

◆ setConcreteMemoryValue() [1/2]

◆ setConcreteMemoryValue() [2/2]

◆ setConcreteRegisterValue()

◆ setMemoryExclusiveTag()

◆ setThumb()

Member Data Documentation

◆ f0

◆ f1

◆ f10

◆ f11

◆ f12

◆ f13

◆ f14

◆ f15

◆ f16

◆ f17

◆ f18

◆ f19

◆ f2

◆ f20

◆ f21

◆ f22

◆ f23

◆ f24

◆ f25

◆ f26

◆ f27

◆ f28

◆ f29

◆ f3

◆ f30

◆ f31

◆ f4

◆ f5

◆ f6

◆ f7

◆ f8

◆ f9

◆ memory