libTriton version 1.0 build 1592
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riscv64Cpu.hpp
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1
2/*
3** Copyright (C) - Triton
4**
5** This program is under the terms of the Apache License 2.0.
6*/
7
8#ifndef TRITON_RISCV64CPU_HPP
9#define TRITON_RISCV64CPU_HPP
10
11#include <set>
12#include <string>
13#include <unordered_map>
14#include <vector>
15
16#include <triton/archEnums.hpp>
17#include <triton/callbacks.hpp>
19#include <triton/dllexport.hpp>
22#include <triton/register.hpp>
25
26
27
29namespace triton {
36 namespace arch {
44 namespace riscv {
52
54
55 static const triton::arch::register_e pcId = triton::arch::ID_REG_RV64_PC;
56 static const triton::arch::register_e spId = triton::arch::ID_REG_RV64_SP;
57
58 private:
61
63 std::size_t handle;
64
66 void copy(const riscv64Cpu& other);
67
69 void disassInit(void);
70
71 protected:
79 std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>> memory;
80
211
213 #define SYS_REG_SPEC(_, LOWER_NAME, _2, _3, _4, _5, _6) \
214 triton::uint8 LOWER_NAME[triton::size::qword];
215 #define REG_SPEC(_1, _2, _3, _4, _5, _6, _7)
216 #define REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6, _7)
217 #include "triton/riscv64.spec"
218
219 public:
221 TRITON_EXPORT riscv64Cpu(triton::callbacks::Callbacks* callbacks=nullptr);
222
224 TRITON_EXPORT riscv64Cpu(const riscv64Cpu& other);
225
227 TRITON_EXPORT virtual ~riscv64Cpu();
228
230 TRITON_EXPORT riscv64Cpu& operator=(const riscv64Cpu& other);
231
233 TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const;
234
236 TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const;
237
238 /* Virtual pure inheritance ================================================= */
239 TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const;
240 TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const;
241 TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const;
242 TRITON_EXPORT bool isThumb(void) const;
243 TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess& mem) const;
244 TRITON_EXPORT const std::unordered_map<triton::arch::register_e, const triton::arch::Register>& getAllRegisters(void) const;
245 TRITON_EXPORT const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>& getConcreteMemory(void) const;
246 TRITON_EXPORT const triton::arch::Register& getParentRegister(const triton::arch::Register& reg) const;
248 TRITON_EXPORT const triton::arch::Register& getProgramCounter(void) const;
249 TRITON_EXPORT const triton::arch::Register& getRegister(triton::arch::register_e id) const;
250 TRITON_EXPORT const triton::arch::Register& getRegister(const std::string& name) const;
251 TRITON_EXPORT const triton::arch::Register& getStackPointer(void) const;
252 TRITON_EXPORT std::set<const triton::arch::Register*> getParentRegisters(void) const;
253 TRITON_EXPORT std::vector<triton::uint8> getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const;
254 TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const;
255 TRITON_EXPORT triton::uint32 numberOfRegisters(void) const;
256 TRITON_EXPORT triton::uint32 gprBitSize(void) const;
257 TRITON_EXPORT triton::uint32 gprSize(void) const;
258 TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess& mem, bool execCallbacks=true) const;
259 TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register& reg, bool execCallbacks=true) const;
260 TRITON_EXPORT triton::uint8 getConcreteMemoryValue(triton::uint64 addr, bool execCallbacks=true) const;
261 TRITON_EXPORT void clear(void);
262 TRITON_EXPORT void disassembly(triton::arch::Instruction& inst);
263 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector<triton::uint8>& values, bool execCallbacks=true);
264 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const void* area, triton::usize size, bool execCallbacks=true);
265 TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess& mem, const triton::uint512& value, bool execCallbacks=true);
266 TRITON_EXPORT void setConcreteMemoryValue(triton::uint64 addr, triton::uint8 value, bool execCallbacks=true);
267 TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register& reg, const triton::uint512& value, bool execCallbacks=true);
268 TRITON_EXPORT void setThumb(bool state);
269 TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess& mem, bool tag);
270 TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess& mem) const;
271 TRITON_EXPORT bool isConcreteMemoryValueDefined(triton::uint64 baseAddr, triton::usize size=1) const;
272 TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess& mem);
273 TRITON_EXPORT void clearConcreteMemoryValue(triton::uint64 baseAddr, triton::usize size=1);
274 /* End of virtual pure inheritance ========================================== */
275 };
276
278 };
280 };
282};
283
284#endif /* TRITON_RISCV64CPU_HPP */
This interface is used as abstract CPU interface. All CPU must use this interface.
This class is used to represent an instruction.
This class is used to represent a memory access.
This class is used when an instruction has a register operand.
Definition register.hpp:44
This class is used to describe the RV64 spec.
triton::uint8 x6[triton::size::qword]
Concrete value of x6.
triton::uint8 f7[triton::size::dqword]
Concrete value of f7.
triton::uint8 f19[triton::size::dqword]
Concrete value of f19.
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
triton::uint8 f9[triton::size::dqword]
Concrete value of f9.
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
TRITON_EXPORT riscv64Cpu(triton::callbacks::Callbacks *callbacks=nullptr)
Constructor.
triton::uint8 x30[triton::size::qword]
Concrete value of x30.
triton::uint8 f12[triton::size::dqword]
Concrete value of f12.
triton::uint8 f11[triton::size::dqword]
Concrete value of f11.
triton::uint8 x15[triton::size::qword]
Concrete value of x15.
triton::uint8 x28[triton::size::qword]
Concrete value of x28.
triton::uint8 x5[triton::size::qword]
Concrete value of x5.
triton::uint8 f4[triton::size::dqword]
Concrete value of f4.
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
triton::uint8 f30[triton::size::dqword]
Concrete value of f30.
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
triton::uint8 x13[triton::size::qword]
Concrete value of x13.
triton::uint8 f21[triton::size::dqword]
Concrete value of f21.
triton::uint8 x17[triton::size::qword]
Concrete value of x17.
triton::uint8 f29[triton::size::dqword]
Concrete value of f29.
triton::uint8 x21[triton::size::qword]
Concrete value of x21.
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
triton::uint8 f17[triton::size::dqword]
Concrete value of f17.
triton::uint8 f15[triton::size::dqword]
Concrete value of f15.
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
triton::uint8 x1[triton::size::qword]
Concrete value of x1.
triton::uint8 x4[triton::size::qword]
Concrete value of x4.
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
triton::uint8 f22[triton::size::dqword]
Concrete value of f22.
triton::uint8 x20[triton::size::qword]
Concrete value of x20.
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
triton::uint8 x14[triton::size::qword]
Concrete value of x14.
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
triton::uint8 x3[triton::size::qword]
Concrete value of x3.
triton::uint8 x18[triton::size::qword]
Concrete value of x18.
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
triton::uint8 f25[triton::size::dqword]
Concrete value of f25.
triton::uint8 f31[triton::size::dqword]
Concrete value of f31.
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const
Returns true if regId is a FPU register.
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
triton::uint8 pc[triton::size::qword]
Concrete value of pc.
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
triton::uint8 x23[triton::size::qword]
Concrete value of x23.
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
triton::uint8 f3[triton::size::dqword]
Concrete value of f3.
triton::uint8 f2[triton::size::dqword]
Concrete value of f2.
triton::uint8 x25[triton::size::qword]
Concrete value of x25.
triton::uint8 x12[triton::size::qword]
Concrete value of x12.
triton::uint8 x7[triton::size::qword]
Concrete value of x7.
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
triton::uint8 f24[triton::size::dqword]
Concrete value of f24.
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
triton::uint8 x22[triton::size::qword]
Concrete value of x22.
triton::uint8 f8[triton::size::dqword]
Concrete value of f8.
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register &reg) const
Returns parent register from a given one.
triton::uint8 x24[triton::size::qword]
Concrete value of x24.
triton::uint8 f1[triton::size::dqword]
Concrete value of f1.
triton::uint8 x29[triton::size::qword]
Concrete value of x29.
triton::uint8 x8[triton::size::qword]
Concrete value of x8.
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
triton::uint8 f20[triton::size::dqword]
Concrete value of f20.
triton::uint8 f10[triton::size::dqword]
Concrete value of f10.
triton::uint8 f18[triton::size::dqword]
Concrete value of f18.
triton::uint8 x31[triton::size::qword]
Concrete value of x31.
triton::uint8 f6[triton::size::dqword]
Concrete value of f6.
triton::uint8 f14[triton::size::dqword]
Concrete value of f14.
triton::uint8 sp[triton::size::qword]
Concrete value of sp.
triton::uint8 f16[triton::size::dqword]
Concrete value of f16.
triton::uint8 x10[triton::size::qword]
Concrete value of x10.
triton::uint8 x19[triton::size::qword]
Concrete value of x19.
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
triton::uint8 f27[triton::size::dqword]
Concrete value of f27.
triton::uint8 x0[triton::size::qword]
Concrete value of x0.
virtual TRITON_EXPORT ~riscv64Cpu()
Destructor.
triton::uint8 f28[triton::size::dqword]
Concrete value of f28.
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
triton::uint8 f0[triton::size::dqword]
Concrete value of f0.
TRITON_EXPORT riscv64Cpu & operator=(const riscv64Cpu &other)
Copies a riscv64Cpu class.
triton::uint8 x27[triton::size::qword]
Concrete value of x27.
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
triton::uint8 x16[triton::size::qword]
Concrete value of x16.
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register &reg, bool execCallbacks=true) const
Returns the concrete value of a register.
triton::uint8 f26[triton::size::dqword]
Concrete value of f26.
triton::uint8 x11[triton::size::qword]
Concrete value of x11.
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
triton::uint8 x9[triton::size::qword]
Concrete value of x9.
triton::uint8 f13[triton::size::dqword]
Concrete value of f13.
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
triton::uint8 f5[triton::size::dqword]
Concrete value of f5.
triton::uint8 x26[triton::size::qword]
Concrete value of x26.
triton::uint8 f23[triton::size::dqword]
Concrete value of f23.
The riscvSpecifications class defines specifications about the RV32 and RV64 CPU.
The callbacks class.
Definition callbacks.hpp:79
register_e
Types of register.
Definition archEnums.hpp:68
constexpr triton::uint32 dqword
dqword size in byte
Definition cpuSize.hpp:40
constexpr triton::uint32 qword
qword size in byte
Definition cpuSize.hpp:36
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits
The Triton namespace.