8#ifndef TRITON_ARM32SPECIFICATIONS_H
9#define TRITON_ARM32SPECIFICATIONS_H
11#include <unordered_map>
57 std::unordered_map<triton::arch::register_e, const triton::arch::Register>
id2reg;
58 std::unordered_map<std::string, triton::arch::register_e> name2id;
This class is used to represent an instruction.
The Arm32Specifications class defines specifications about the Arm32 CPU.
std::unordered_map< triton::arch::register_e, const triton::arch::Register > id2reg
List of registers specification available for this architecture.
TRITON_EXPORT triton::arch::register_e capstoneRegisterToTritonRegister(triton::uint32 id) const
Converts a capstone's register id to a triton's register id.
TRITON_EXPORT triton::uint32 capstoneInstructionToTritonInstruction(triton::uint32 id) const
Converts a capstone's instruction id to a triton's instruction id.
TRITON_EXPORT triton::arch::arm::shift_e capstoneShiftToTritonShift(triton::uint32 id) const
Converts a capstone's shift id to a triton's shift id.
TRITON_EXPORT triton::arch::arm::condition_e capstoneConditionToTritonCondition(triton::uint32 id) const
Converts a capstone's condition id to a triton's condition id.
TRITON_EXPORT Arm32Specifications(triton::arch::architecture_e)
Constructor.
TRITON_EXPORT triton::uint32 getMemoryOperandSpecialSize(triton::uint32 id) const
Returns memory access size if it is specified by instruction.
register_e
Types of register.
instruction_e
The list of opcodes.
const triton::arch::Instruction nop
ARM32 NOP instruction.
const triton::arch::Instruction thumbnop
ARM32 Thumb NOP instruction.
@ ID_INS_VQRDMULH
vqrdmulh
@ ID_INS_VQRSHRUN
vqrshrun
@ ID_INS_SHA256SU1
sha256su1
@ ID_INS_SHA256SU0
sha256su0
@ ID_INS_SHA256H2
sha256h2
@ ID_INS_LAST_ITEM
must be the last item
condition_e
Types of condition.
std::uint32_t uint32
unisgned 32-bits