libTriton version 1.0 build 1592
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This class is used to describe the x86 (32-bits) spec. More...
#include <x86Cpu.hpp>
Public Member Functions | |
TRITON_EXPORT | x86Cpu (triton::callbacks::Callbacks *callbacks=nullptr) |
Constructor. | |
TRITON_EXPORT | x86Cpu (const x86Cpu &other) |
Copy constructor. | |
virtual TRITON_EXPORT | ~x86Cpu () |
Destructor. | |
TRITON_EXPORT x86Cpu & | operator= (const x86Cpu &other) |
Copies a x86Cpu class. | |
TRITON_EXPORT bool | isGPR (triton::arch::register_e regId) const |
Returns true if regId is a GRP. | |
TRITON_EXPORT bool | isMMX (triton::arch::register_e regId) const |
Returns true if regId is a MMX register. | |
TRITON_EXPORT bool | isSTX (triton::arch::register_e regId) const |
Returns true if regId is a STX register. | |
TRITON_EXPORT bool | isSSECTL (triton::arch::register_e regId) const |
Returns true if regId is a SSE Contol register. | |
TRITON_EXPORT bool | isSSE (triton::arch::register_e regId) const |
Returns true if regId is a SSE register. | |
TRITON_EXPORT bool | isFPU (triton::arch::register_e regId) const |
Returns true if regId is a FPU register. | |
TRITON_EXPORT bool | isEFER (triton::arch::register_e regId) const |
Returns true if regId is an EFER register. | |
TRITON_EXPORT bool | isTSC (triton::arch::register_e regId) const |
Returns true if regId is an TSC register. | |
TRITON_EXPORT bool | isAVX256 (triton::arch::register_e regId) const |
Returns true if regId is a AVX-256 (YMM) register. | |
TRITON_EXPORT bool | isControl (triton::arch::register_e regId) const |
Returns true if regId is a control (cr) register. | |
TRITON_EXPORT bool | isDebug (triton::arch::register_e regId) const |
Returns true if regId is a debug (dr) register. | |
TRITON_EXPORT bool | isSegment (triton::arch::register_e regId) const |
Returns true if regId is a Segment. | |
TRITON_EXPORT bool | isFlag (triton::arch::register_e regId) const |
Returns true if the register ID is a flag. | |
TRITON_EXPORT bool | isRegister (triton::arch::register_e regId) const |
Returns true if the register ID is a register. | |
TRITON_EXPORT bool | isRegisterValid (triton::arch::register_e regId) const |
Returns true if the register ID is valid. | |
TRITON_EXPORT bool | isThumb (void) const |
Returns true if the execution mode is Thumb. Only useful for Arm32. | |
TRITON_EXPORT bool | isMemoryExclusive (const triton::arch::MemoryAccess &mem) const |
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64. | |
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & | getAllRegisters (void) const |
Returns all registers. | |
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & | getConcreteMemory (void) const |
Return all memory. | |
TRITON_EXPORT const triton::arch::Register & | getParentRegister (const triton::arch::Register ®) const |
Returns parent register from a given one. | |
TRITON_EXPORT const triton::arch::Register & | getParentRegister (triton::arch::register_e id) const |
Returns parent register from a given one. | |
TRITON_EXPORT const triton::arch::Register & | getProgramCounter (void) const |
Returns the program counter register. | |
TRITON_EXPORT const triton::arch::Register & | getRegister (triton::arch::register_e id) const |
Returns register from id. | |
TRITON_EXPORT const triton::arch::Register & | getRegister (const std::string &name) const |
Returns register from name. | |
TRITON_EXPORT const triton::arch::Register & | getStackPointer (void) const |
Returns the stack pointer register. | |
TRITON_EXPORT std::set< const triton::arch::Register * > | getParentRegisters (void) const |
Returns all parent registers. | |
TRITON_EXPORT std::vector< triton::uint8 > | getConcreteMemoryAreaValue (triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const |
Returns the concrete value of a memory area. | |
TRITON_EXPORT triton::arch::endianness_e | getEndianness (void) const |
Returns the kind of endianness as triton::arch::endianness_e. | |
TRITON_EXPORT triton::uint32 | numberOfRegisters (void) const |
Returns the number of registers according to the CPU architecture. | |
TRITON_EXPORT triton::uint32 | gprBitSize (void) const |
Returns the bit in bit of the General Purpose Registers. | |
TRITON_EXPORT triton::uint32 | gprSize (void) const |
Returns the bit in byte of the General Purpose Registers. | |
TRITON_EXPORT triton::uint512 | getConcreteMemoryValue (const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const |
Returns the concrete value of memory cells. | |
TRITON_EXPORT triton::uint512 | getConcreteRegisterValue (const triton::arch::Register ®, bool execCallbacks=true) const |
Returns the concrete value of a register. | |
TRITON_EXPORT triton::uint8 | getConcreteMemoryValue (triton::uint64 addr, bool execCallbacks=true) const |
Returns the concrete value of a memory cell. | |
TRITON_EXPORT void | clear (void) |
Clears the architecture states (registers and memory). | |
TRITON_EXPORT void | disassembly (triton::arch::Instruction &inst) |
Disassembles the instruction according to the architecture. | |
TRITON_EXPORT void | setConcreteMemoryAreaValue (triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory area. | |
TRITON_EXPORT void | setConcreteMemoryAreaValue (triton::uint64 baseAddr, const void *area, triton::usize size, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory area. | |
TRITON_EXPORT void | setConcreteMemoryValue (const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of memory cells. | |
TRITON_EXPORT void | setConcreteMemoryValue (triton::uint64 addr, triton::uint8 value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a memory cell. | |
TRITON_EXPORT void | setConcreteRegisterValue (const triton::arch::Register ®, const triton::uint512 &value, bool execCallbacks=true) |
[architecture api] - Sets the concrete value of a register. | |
TRITON_EXPORT void | setThumb (bool state) |
Sets CPU state to Thumb mode. | |
TRITON_EXPORT void | setMemoryExclusiveTag (const triton::arch::MemoryAccess &mem, bool tag) |
Sets exclusive memory access tag. Only valid for Arm32 and AArch64. | |
TRITON_EXPORT bool | isConcreteMemoryValueDefined (const triton::arch::MemoryAccess &mem) const |
Returns true if memory cells have a defined concrete value. | |
TRITON_EXPORT bool | isConcreteMemoryValueDefined (triton::uint64 baseAddr, triton::usize size=1) const |
Returns true if memory cells have a defined concrete value. | |
TRITON_EXPORT void | clearConcreteMemoryValue (const triton::arch::MemoryAccess &mem) |
Clears concrete values assigned to the memory cells. | |
TRITON_EXPORT void | clearConcreteMemoryValue (triton::uint64 baseAddr, triton::usize size=1) |
Clears concrete values assigned to the memory cells. | |
Public Member Functions inherited from triton::arch::CpuInterface | |
virtual TRITON_EXPORT | ~CpuInterface () |
Destructor. | |
Public Member Functions inherited from triton::arch::x86::x86Specifications | |
TRITON_EXPORT | x86Specifications (triton::arch::architecture_e) |
Constructor. | |
TRITON_EXPORT triton::arch::register_e | capstoneRegisterToTritonRegister (triton::uint32 id) const |
Converts a capstone's register id to a triton's register id. | |
TRITON_EXPORT triton::uint32 | capstoneInstructionToTritonInstruction (triton::uint32 id) const |
Converts a capstone's instruction id to a triton's instruction id. | |
TRITON_EXPORT triton::arch::x86::prefix_e | capstonePrefixToTritonPrefix (triton::uint32 id) const |
Converts a capstone's prefix id to a triton's prefix id. | |
This class is used to describe the x86 (32-bits) spec.
Definition at line 53 of file x86Cpu.hpp.
triton::arch::x86::x86Cpu::x86Cpu | ( | triton::callbacks::Callbacks * | callbacks = nullptr | ) |
Constructor.
Definition at line 26 of file x86Cpu.cpp.
triton::arch::x86::x86Cpu::x86Cpu | ( | const x86Cpu & | other | ) |
Copy constructor.
Definition at line 35 of file x86Cpu.cpp.
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Destructor.
Definition at line 40 of file x86Cpu.cpp.
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Clears the architecture states (registers and memory).
Implements triton::arch::CpuInterface.
Definition at line 134 of file x86Cpu.cpp.
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Clears concrete values assigned to the memory cells.
Implements triton::arch::CpuInterface.
Definition at line 1507 of file x86Cpu.cpp.
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Clears concrete values assigned to the memory cells.
Implements triton::arch::CpuInterface.
Definition at line 1512 of file x86Cpu.cpp.
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Disassembles the instruction according to the architecture.
Implements triton::arch::CpuInterface.
Definition at line 432 of file x86Cpu.cpp.
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Returns all registers.
Implements triton::arch::CpuInterface.
Definition at line 328 of file x86Cpu.cpp.
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Return all memory.
Implements triton::arch::CpuInterface.
Definition at line 332 of file x86Cpu.cpp.
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Returns the concrete value of a memory area.
Implements triton::arch::CpuInterface.
Definition at line 579 of file x86Cpu.cpp.
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Returns the concrete value of memory cells.
Implements triton::arch::CpuInterface.
Definition at line 558 of file x86Cpu.cpp.
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Returns the concrete value of a memory cell.
Implements triton::arch::CpuInterface.
Definition at line 545 of file x86Cpu.cpp.
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Returns the concrete value of a register.
Implements triton::arch::CpuInterface.
Definition at line 589 of file x86Cpu.cpp.
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Returns the kind of endianness as triton::arch::endianness_e.
Implements triton::arch::CpuInterface.
Definition at line 214 of file x86Cpu.cpp.
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Returns parent register from a given one.
Implements triton::arch::CpuInterface.
Definition at line 412 of file x86Cpu.cpp.
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Returns parent register from a given one.
Implements triton::arch::CpuInterface.
Definition at line 417 of file x86Cpu.cpp.
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Returns all parent registers.
Implements triton::arch::CpuInterface.
Definition at line 337 of file x86Cpu.cpp.
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Returns the program counter register.
Implements triton::arch::CpuInterface.
Definition at line 422 of file x86Cpu.cpp.
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Returns register from name.
Implements triton::arch::CpuInterface.
Definition at line 401 of file x86Cpu.cpp.
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Returns register from id.
Implements triton::arch::CpuInterface.
Definition at line 392 of file x86Cpu.cpp.
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Returns the stack pointer register.
Implements triton::arch::CpuInterface.
Definition at line 427 of file x86Cpu.cpp.
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Returns the bit in bit of the General Purpose Registers.
Implements triton::arch::CpuInterface.
Definition at line 322 of file x86Cpu.cpp.
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Returns the bit in byte of the General Purpose Registers.
Implements triton::arch::CpuInterface.
Definition at line 317 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isAVX256 | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a AVX-256 (YMM) register.
Definition at line 292 of file x86Cpu.cpp.
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Returns true if memory cells have a defined concrete value.
Implements triton::arch::CpuInterface.
Definition at line 1492 of file x86Cpu.cpp.
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Returns true if memory cells have a defined concrete value.
Implements triton::arch::CpuInterface.
Definition at line 1497 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isControl | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a control (cr) register.
Definition at line 297 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isDebug | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a debug (dr) register.
Definition at line 302 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isEFER | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is an EFER register.
Definition at line 282 of file x86Cpu.cpp.
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Returns true if the register ID is a flag.
Implements triton::arch::CpuInterface.
Definition at line 219 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isFPU | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a FPU register.
Definition at line 277 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isGPR | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a GRP.
Definition at line 252 of file x86Cpu.cpp.
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Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
Implements triton::arch::CpuInterface.
Definition at line 1481 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isMMX | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a MMX register.
Definition at line 257 of file x86Cpu.cpp.
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Returns true if the register ID is a register.
Implements triton::arch::CpuInterface.
Definition at line 229 of file x86Cpu.cpp.
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Returns true if the register ID is valid.
Implements triton::arch::CpuInterface.
Definition at line 247 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isSegment | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a Segment.
Definition at line 307 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isSSE | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a SSE register.
Definition at line 267 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isSSECTL | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a SSE Contol register.
Definition at line 272 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isSTX | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is a STX register.
Definition at line 262 of file x86Cpu.cpp.
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Returns true if the execution mode is Thumb. Only useful for Arm32.
Implements triton::arch::CpuInterface.
Definition at line 1470 of file x86Cpu.cpp.
bool triton::arch::x86::x86Cpu::isTSC | ( | triton::arch::register_e | regId | ) | const |
Returns true if regId is an TSC register.
Definition at line 287 of file x86Cpu.cpp.
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Returns the number of registers according to the CPU architecture.
Implements triton::arch::CpuInterface.
Definition at line 312 of file x86Cpu.cpp.
Copies a x86Cpu class.
Definition at line 208 of file x86Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory area.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 824 of file x86Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory area.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 832 of file x86Cpu.cpp.
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[architecture api] - Sets the concrete value of memory cells.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 803 of file x86Cpu.cpp.
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[architecture api] - Sets the concrete value of a memory cell.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 796 of file x86Cpu.cpp.
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[architecture api] - Sets the concrete value of a register.
Note that by setting a concrete value will probably imply a desynchronization with the symbolic state (if it exists). You should probably use the concretize functions after this.
Implements triton::arch::CpuInterface.
Definition at line 840 of file x86Cpu.cpp.
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Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
Implements triton::arch::CpuInterface.
Definition at line 1487 of file x86Cpu.cpp.
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Sets CPU state to Thumb mode.
Implements triton::arch::CpuInterface.
Definition at line 1476 of file x86Cpu.cpp.
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Concrete value of cr0.
Definition at line 134 of file x86Cpu.hpp.
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Concrete value of cr1.
Definition at line 136 of file x86Cpu.hpp.
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Concrete value of cr10.
Definition at line 154 of file x86Cpu.hpp.
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Concrete value of cr11.
Definition at line 156 of file x86Cpu.hpp.
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Concrete value of cr12.
Definition at line 158 of file x86Cpu.hpp.
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Concrete value of cr13.
Definition at line 160 of file x86Cpu.hpp.
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Concrete value of cr14.
Definition at line 162 of file x86Cpu.hpp.
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Concrete value of cr15.
Definition at line 164 of file x86Cpu.hpp.
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Concrete value of cr2.
Definition at line 138 of file x86Cpu.hpp.
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Concrete value of cr3.
Definition at line 140 of file x86Cpu.hpp.
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Concrete value of cr4.
Definition at line 142 of file x86Cpu.hpp.
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Concrete value of cr5.
Definition at line 144 of file x86Cpu.hpp.
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Concrete value of cr6.
Definition at line 146 of file x86Cpu.hpp.
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Concrete value of cr7.
Definition at line 148 of file x86Cpu.hpp.
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Concrete value of cr8.
Definition at line 150 of file x86Cpu.hpp.
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Concrete value of cr9.
Definition at line 152 of file x86Cpu.hpp.
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Concrete value of CS.
Definition at line 166 of file x86Cpu.hpp.
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Concrete value of dr0.
Definition at line 178 of file x86Cpu.hpp.
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Condete value of dr1.
Definition at line 180 of file x86Cpu.hpp.
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Condete value of dr2.
Definition at line 182 of file x86Cpu.hpp.
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Condete value of dr3.
Definition at line 184 of file x86Cpu.hpp.
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Condete value of dr6.
Definition at line 186 of file x86Cpu.hpp.
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Condete value of dr7.
Definition at line 188 of file x86Cpu.hpp.
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Concrete value of DS.
Definition at line 168 of file x86Cpu.hpp.
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Concrete value of eax.
Definition at line 82 of file x86Cpu.hpp.
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Concrete value of ebp.
Definition at line 94 of file x86Cpu.hpp.
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Concrete value of ebx.
Definition at line 84 of file x86Cpu.hpp.
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Concrete value of ecx.
Definition at line 86 of file x86Cpu.hpp.
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Concrete value of edi.
Definition at line 90 of file x86Cpu.hpp.
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Concrete value of edx.
Definition at line 88 of file x86Cpu.hpp.
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Concrete value of the EFER MSR Register.
Definition at line 206 of file x86Cpu.hpp.
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Concrete value of eflags.
Definition at line 100 of file x86Cpu.hpp.
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Concrete value of eip.
Definition at line 98 of file x86Cpu.hpp.
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Concrete value of ES.
Definition at line 170 of file x86Cpu.hpp.
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Concrete value of esi.
Definition at line 92 of file x86Cpu.hpp.
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Concrete value of esp.
Definition at line 96 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Instruction Pointer Selector.
Definition at line 200 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Control Word.
Definition at line 190 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Instruction Operand Pointer Offset.
Definition at line 202 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Instruction Operand Pointer Selector.
Definition at line 204 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Instruction Pointer Offset.
Definition at line 198 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Opcode.
Definition at line 196 of file x86Cpu.hpp.
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Concrete value of FS.
Definition at line 172 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Status Word.
Definition at line 192 of file x86Cpu.hpp.
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Concrete value of the x87 FPU Tag Word.
Definition at line 194 of file x86Cpu.hpp.
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Concrete value of GS.
Definition at line 174 of file x86Cpu.hpp.
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map of address -> concrete value
item1: memory address
item2: concrete value
Definition at line 79 of file x86Cpu.hpp.
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Concrete value of the SSE Register State.
Definition at line 208 of file x86Cpu.hpp.
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Concrete value of the SSE Register State Mask.
Definition at line 210 of file x86Cpu.hpp.
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Concrete value of SS.
Definition at line 176 of file x86Cpu.hpp.
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Concrete value of st0.
Definition at line 102 of file x86Cpu.hpp.
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Concrete value of st1.
Definition at line 104 of file x86Cpu.hpp.
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Concrete value of st2.
Definition at line 106 of file x86Cpu.hpp.
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Concrete value of st3.
Definition at line 108 of file x86Cpu.hpp.
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Concrete value of st4.
Definition at line 110 of file x86Cpu.hpp.
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Concrete value of st5.
Definition at line 112 of file x86Cpu.hpp.
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Concrete value of st6.
Definition at line 114 of file x86Cpu.hpp.
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Concrete value of st7.
Definition at line 116 of file x86Cpu.hpp.
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Concrete value of the TSC Register.
Definition at line 212 of file x86Cpu.hpp.
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Concrete value of ymm0.
Definition at line 118 of file x86Cpu.hpp.
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Concrete value of ymm1.
Definition at line 120 of file x86Cpu.hpp.
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Concrete value of ymm2.
Definition at line 122 of file x86Cpu.hpp.
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Concrete value of ymm3.
Definition at line 124 of file x86Cpu.hpp.
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Concrete value of ymm4.
Definition at line 126 of file x86Cpu.hpp.
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Concrete value of ymm5.
Definition at line 128 of file x86Cpu.hpp.
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Concrete value of ymm6.
Definition at line 130 of file x86Cpu.hpp.
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Concrete value of ymm7.
Definition at line 132 of file x86Cpu.hpp.