libTriton version 1.0 build 1592
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3** Copyright (C) - Triton
5** This program is under the terms of the Apache License 2.0.
8#ifndef TRITON_X86CPU_HPP
9#define TRITON_X86CPU_HPP
11#include <set>
12#include <string>
13#include <unordered_map>
14#include <vector>
16#include <triton/archEnums.hpp>
17#include <triton/callbacks.hpp>
19#include <triton/dllexport.hpp>
22#include <triton/register.hpp>
29namespace triton {
36 namespace arch {
44 namespace x86 {
53 class x86Cpu : public CpuInterface, public x86Specifications {
55 static const triton::arch::register_e pcId = triton::arch::ID_REG_X86_EIP;
56 static const triton::arch::register_e spId = triton::arch::ID_REG_X86_ESP;
58 private:
63 std::size_t handle;
66 void copy(const x86Cpu& other);
69 void disassInit(void);
71 protected:
79 std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>> memory;
214 public:
216 TRITON_EXPORT x86Cpu(triton::callbacks::Callbacks* callbacks=nullptr);
219 TRITON_EXPORT x86Cpu(const x86Cpu& other);
222 TRITON_EXPORT virtual ~x86Cpu();
225 TRITON_EXPORT x86Cpu& operator=(const x86Cpu& other);
228 TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const;
231 TRITON_EXPORT bool isMMX(triton::arch::register_e regId) const;
234 TRITON_EXPORT bool isSTX(triton::arch::register_e regId) const;
237 TRITON_EXPORT bool isSSECTL(triton::arch::register_e regId) const;
240 TRITON_EXPORT bool isSSE(triton::arch::register_e regId) const;
243 TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const;
246 TRITON_EXPORT bool isEFER(triton::arch::register_e regId) const;
249 TRITON_EXPORT bool isTSC(triton::arch::register_e regId) const;
252 TRITON_EXPORT bool isAVX256(triton::arch::register_e regId) const;
255 TRITON_EXPORT bool isControl(triton::arch::register_e regId) const;
258 TRITON_EXPORT bool isDebug(triton::arch::register_e regId) const;
261 TRITON_EXPORT bool isSegment(triton::arch::register_e regId) const;
263 /* Virtual pure inheritance ================================================= */
264 TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const;
265 TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const;
266 TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const;
267 TRITON_EXPORT bool isThumb(void) const;
268 TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess& mem) const;
269 TRITON_EXPORT const std::unordered_map<triton::arch::register_e, const triton::arch::Register>& getAllRegisters(void) const;
270 TRITON_EXPORT const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>& getConcreteMemory(void) const;
271 TRITON_EXPORT const triton::arch::Register& getParentRegister(const triton::arch::Register& reg) const;
273 TRITON_EXPORT const triton::arch::Register& getProgramCounter(void) const;
274 TRITON_EXPORT const triton::arch::Register& getRegister(triton::arch::register_e id) const;
275 TRITON_EXPORT const triton::arch::Register& getRegister(const std::string& name) const;
276 TRITON_EXPORT const triton::arch::Register& getStackPointer(void) const;
277 TRITON_EXPORT std::set<const triton::arch::Register*> getParentRegisters(void) const;
278 TRITON_EXPORT std::vector<triton::uint8> getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const;
279 TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const;
280 TRITON_EXPORT triton::uint32 numberOfRegisters(void) const;
281 TRITON_EXPORT triton::uint32 gprBitSize(void) const;
282 TRITON_EXPORT triton::uint32 gprSize(void) const;
283 TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess& mem, bool execCallbacks=true) const;
284 TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register& reg, bool execCallbacks=true) const;
285 TRITON_EXPORT triton::uint8 getConcreteMemoryValue(triton::uint64 addr, bool execCallbacks=true) const;
286 TRITON_EXPORT void clear(void);
287 TRITON_EXPORT void disassembly(triton::arch::Instruction& inst);
288 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector<triton::uint8>& values, bool execCallbacks=true);
289 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const void* area, triton::usize size, bool execCallbacks=true);
290 TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess& mem, const triton::uint512& value, bool execCallbacks=true);
291 TRITON_EXPORT void setConcreteMemoryValue(triton::uint64 addr, triton::uint8 value, bool execCallbacks=true);
292 TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register& reg, const triton::uint512& value, bool execCallbacks=true);
293 TRITON_EXPORT void setThumb(bool state);
294 TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess& mem, bool tag);
295 TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess& mem) const;
296 TRITON_EXPORT bool isConcreteMemoryValueDefined(triton::uint64 baseAddr, triton::usize size=1) const;
297 TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess& mem);
298 TRITON_EXPORT void clearConcreteMemoryValue(triton::uint64 baseAddr, triton::usize size=1);
299 /* End of virtual pure inheritance ========================================== */
300 };
303 };
305 };
309#endif /* TRITON_X86CPU_HPP */
This interface is used as abstract CPU interface. All CPU must use this interface.
This class is used to represent an instruction.
This class is used to represent a memory access.
This class is used when an instruction has a register operand.
Definition register.hpp:44
This class is used to describe the x86 (32-bits) spec.
Definition x86Cpu.hpp:53
triton::uint8 cr5[triton::size::dword]
Concrete value of cr5.
Definition x86Cpu.hpp:144
triton::uint8 dr2[triton::size::dword]
Condete value of dr2.
Definition x86Cpu.hpp:182
triton::uint8 dr1[triton::size::dword]
Condete value of dr1.
Definition x86Cpu.hpp:180
triton::uint8 efer[triton::size::qword]
Concrete value of the EFER MSR Register.
Definition x86Cpu.hpp:206
triton::uint8 st1[triton::size::fword]
Concrete value of st1.
Definition x86Cpu.hpp:104
triton::uint8 dr7[triton::size::dword]
Condete value of dr7.
Definition x86Cpu.hpp:188
triton::uint8 tsc[triton::size::qword]
Concrete value of the TSC Register.
Definition x86Cpu.hpp:212
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
Definition x86Cpu.cpp:317
triton::uint8 gs[triton::size::dword]
Concrete value of GS.
Definition x86Cpu.hpp:174
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
Definition x86Cpu.cpp:229
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
Definition x86Cpu.cpp:840
TRITON_EXPORT bool isSTX(triton::arch::register_e regId) const
Returns true if regId is a STX register.
Definition x86Cpu.cpp:262
triton::uint8 dr3[triton::size::dword]
Condete value of dr3.
Definition x86Cpu.hpp:184
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
Definition x86Cpu.cpp:579
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
Definition x86Cpu.cpp:432
virtual TRITON_EXPORT ~x86Cpu()
Definition x86Cpu.cpp:40
triton::uint8 cr9[triton::size::dword]
Concrete value of cr9.
Definition x86Cpu.hpp:152
triton::uint8 mxcsr[triton::size::dword]
Concrete value of the SSE Register State.
Definition x86Cpu.hpp:208
triton::uint8 st7[triton::size::fword]
Concrete value of st7.
Definition x86Cpu.hpp:116
triton::uint8 fds[triton::size::word]
Concrete value of the x87 FPU Instruction Operand Pointer Selector.
Definition x86Cpu.hpp:204
triton::uint8 ebx[triton::size::dword]
Concrete value of ebx.
Definition x86Cpu.hpp:84
triton::uint8 fdp[triton::size::qword]
Concrete value of the x87 FPU Instruction Operand Pointer Offset.
Definition x86Cpu.hpp:202
triton::uint8 st6[triton::size::fword]
Concrete value of st6.
Definition x86Cpu.hpp:114
TRITON_EXPORT bool isSegment(triton::arch::register_e regId) const
Returns true if regId is a Segment.
Definition x86Cpu.cpp:307
TRITON_EXPORT x86Cpu(triton::callbacks::Callbacks *callbacks=nullptr)
Definition x86Cpu.cpp:26
TRITON_EXPORT bool isEFER(triton::arch::register_e regId) const
Returns true if regId is an EFER register.
Definition x86Cpu.cpp:282
triton::uint8 st4[triton::size::fword]
Concrete value of st4.
Definition x86Cpu.hpp:110
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
Definition x86Cpu.cpp:322
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
Definition x86Cpu.cpp:214
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
Definition x86Cpu.cpp:1487
triton::uint8 fop[triton::size::word]
Concrete value of the x87 FPU Opcode.
Definition x86Cpu.hpp:196
triton::uint8 cr7[triton::size::dword]
Concrete value of cr7.
Definition x86Cpu.hpp:148
triton::uint8 ebp[triton::size::dword]
Concrete value of ebp.
Definition x86Cpu.hpp:94
TRITON_EXPORT bool isAVX256(triton::arch::register_e regId) const
Returns true if regId is a AVX-256 (YMM) register.
Definition x86Cpu.cpp:292
triton::uint8 ymm3[triton::size::qqword]
Concrete value of ymm3.
Definition x86Cpu.hpp:124
triton::uint8 cr13[triton::size::dword]
Concrete value of cr13.
Definition x86Cpu.hpp:160
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
Definition x86Cpu.cpp:422
TRITON_EXPORT bool isControl(triton::arch::register_e regId) const
Returns true if regId is a control (cr) register.
Definition x86Cpu.cpp:297
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
Definition x86Cpu.cpp:312
triton::uint8 ftw[triton::size::word]
Concrete value of the x87 FPU Tag Word.
Definition x86Cpu.hpp:194
triton::uint8 fcw[triton::size::word]
Concrete value of the x87 FPU Control Word.
Definition x86Cpu.hpp:190
TRITON_EXPORT bool isSSE(triton::arch::register_e regId) const
Returns true if regId is a SSE register.
Definition x86Cpu.cpp:267
triton::uint8 st5[triton::size::fword]
Concrete value of st5.
Definition x86Cpu.hpp:112
triton::uint8 fsw[triton::size::word]
Concrete value of the x87 FPU Status Word.
Definition x86Cpu.hpp:192
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
Definition x86Cpu.cpp:252
triton::uint8 ymm4[triton::size::qqword]
Concrete value of ymm4.
Definition x86Cpu.hpp:126
triton::uint8 ymm7[triton::size::qqword]
Concrete value of ymm7.
Definition x86Cpu.hpp:132
triton::uint8 cs[triton::size::dword]
Concrete value of CS.
Definition x86Cpu.hpp:166
TRITON_EXPORT x86Cpu & operator=(const x86Cpu &other)
Copies a x86Cpu class.
Definition x86Cpu.cpp:208
triton::uint8 esi[triton::size::dword]
Concrete value of esi.
Definition x86Cpu.hpp:92
triton::uint8 ds[triton::size::dword]
Concrete value of DS.
Definition x86Cpu.hpp:168
TRITON_EXPORT bool isTSC(triton::arch::register_e regId) const
Returns true if regId is an TSC register.
Definition x86Cpu.cpp:287
triton::uint8 mxcsr_mask[triton::size::dword]
Concrete value of the SSE Register State Mask.
Definition x86Cpu.hpp:210
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
Definition x86Cpu.cpp:803
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
Definition x86Cpu.cpp:337
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
Definition x86Cpu.cpp:1507
triton::uint8 ymm0[triton::size::qqword]
Concrete value of ymm0.
Definition x86Cpu.hpp:118
triton::uint8 edi[triton::size::dword]
Concrete value of edi.
Definition x86Cpu.hpp:90
triton::uint8 cr4[triton::size::dword]
Concrete value of cr4.
Definition x86Cpu.hpp:142
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
Definition x86Cpu.cpp:1476
triton::uint8 fcs[triton::size::word]
Concrete value of the x87 FPU Instruction Pointer Selector.
Definition x86Cpu.hpp:200
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
Definition x86Cpu.cpp:558
triton::uint8 ss[triton::size::dword]
Concrete value of SS.
Definition x86Cpu.hpp:176
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register &reg) const
Returns parent register from a given one.
Definition x86Cpu.cpp:412
triton::uint8 es[triton::size::dword]
Concrete value of ES.
Definition x86Cpu.hpp:170
triton::uint8 st2[triton::size::fword]
Concrete value of st2.
Definition x86Cpu.hpp:106
triton::uint8 eax[triton::size::dword]
Concrete value of eax.
Definition x86Cpu.hpp:82
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
Definition x86Cpu.hpp:79
triton::uint8 dr0[triton::size::dword]
Concrete value of dr0.
Definition x86Cpu.hpp:178
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register &reg, bool execCallbacks=true) const
Returns the concrete value of a register.
Definition x86Cpu.cpp:589
TRITON_EXPORT bool isSSECTL(triton::arch::register_e regId) const
Returns true if regId is a SSE Contol register.
Definition x86Cpu.cpp:272
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
Definition x86Cpu.cpp:1481
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
Definition x86Cpu.cpp:392
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
Definition x86Cpu.cpp:1470
triton::uint8 esp[triton::size::dword]
Concrete value of esp.
Definition x86Cpu.hpp:96
triton::uint8 st3[triton::size::fword]
Concrete value of st3.
Definition x86Cpu.hpp:108
triton::uint8 st0[triton::size::fword]
Concrete value of st0.
Definition x86Cpu.hpp:102
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
Definition x86Cpu.cpp:134
triton::uint8 ymm5[triton::size::qqword]
Concrete value of ymm5.
Definition x86Cpu.hpp:128
triton::uint8 cr1[triton::size::dword]
Concrete value of cr1.
Definition x86Cpu.hpp:136
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
Definition x86Cpu.cpp:1492
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
Definition x86Cpu.cpp:824
triton::uint8 ymm6[triton::size::qqword]
Concrete value of ymm6.
Definition x86Cpu.hpp:130
triton::uint8 eip[triton::size::dword]
Concrete value of eip.
Definition x86Cpu.hpp:98
triton::uint8 ecx[triton::size::dword]
Concrete value of ecx.
Definition x86Cpu.hpp:86
triton::uint8 dr6[triton::size::dword]
Condete value of dr6.
Definition x86Cpu.hpp:186
triton::uint8 cr15[triton::size::dword]
Concrete value of cr15.
Definition x86Cpu.hpp:164
triton::uint8 cr11[triton::size::dword]
Concrete value of cr11.
Definition x86Cpu.hpp:156
triton::uint8 fs[triton::size::dword]
Concrete value of FS.
Definition x86Cpu.hpp:172
triton::uint8 ymm1[triton::size::qqword]
Concrete value of ymm1.
Definition x86Cpu.hpp:120
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
Definition x86Cpu.cpp:328
triton::uint8 cr2[triton::size::dword]
Concrete value of cr2.
Definition x86Cpu.hpp:138
TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const
Returns true if regId is a FPU register.
Definition x86Cpu.cpp:277
triton::uint8 cr8[triton::size::dword]
Concrete value of cr8.
Definition x86Cpu.hpp:150
TRITON_EXPORT bool isDebug(triton::arch::register_e regId) const
Returns true if regId is a debug (dr) register.
Definition x86Cpu.cpp:302
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
Definition x86Cpu.cpp:427
triton::uint8 fip[triton::size::qword]
Concrete value of the x87 FPU Instruction Pointer Offset.
Definition x86Cpu.hpp:198
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
Definition x86Cpu.cpp:332
TRITON_EXPORT bool isMMX(triton::arch::register_e regId) const
Returns true if regId is a MMX register.
Definition x86Cpu.cpp:257
triton::uint8 cr10[triton::size::dword]
Concrete value of cr10.
Definition x86Cpu.hpp:154
triton::uint8 ymm2[triton::size::qqword]
Concrete value of ymm2.
Definition x86Cpu.hpp:122
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
Definition x86Cpu.cpp:247
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
Definition x86Cpu.cpp:219
triton::uint8 cr14[triton::size::dword]
Concrete value of cr14.
Definition x86Cpu.hpp:162
triton::uint8 cr12[triton::size::dword]
Concrete value of cr12.
Definition x86Cpu.hpp:158
triton::uint8 cr0[triton::size::dword]
Concrete value of cr0.
Definition x86Cpu.hpp:134
triton::uint8 cr6[triton::size::dword]
Concrete value of cr6.
Definition x86Cpu.hpp:146
triton::uint8 cr3[triton::size::dword]
Concrete value of cr3.
Definition x86Cpu.hpp:140
triton::uint8 eflags[triton::size::dword]
Concrete value of eflags.
Definition x86Cpu.hpp:100
triton::uint8 edx[triton::size::dword]
Concrete value of edx.
Definition x86Cpu.hpp:88
The x86Specifications class defines specifications about the x86 and x86_64 CPU.
The callbacks class.
Definition callbacks.hpp:79
Types of register.
Definition archEnums.hpp:64
constexpr triton::uint32 fword
fword size in byte
Definition cpuSize.hpp:38
constexpr triton::uint32 dword
dword size in byte
Definition cpuSize.hpp:34
constexpr triton::uint32 word
word size in byte
Definition cpuSize.hpp:32
constexpr triton::uint32 qword
qword size in byte
Definition cpuSize.hpp:36
constexpr triton::uint32 qqword
qqword size in byte
Definition cpuSize.hpp:42
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits
The Triton namespace.