8#ifndef TRITON_X86CPU_HPP
9#define TRITON_X86CPU_HPP
13#include <unordered_map>
66 void copy(
const x86Cpu& other);
69 void disassInit(
void);
79 std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>
memory;
222 TRITON_EXPORT
virtual ~x86Cpu();
267 TRITON_EXPORT
bool isThumb(
void)
const;
269 TRITON_EXPORT
const std::unordered_map<triton::arch::register_e, const triton::arch::Register>&
getAllRegisters(
void)
const;
270 TRITON_EXPORT
const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>&
getConcreteMemory(
void)
const;
286 TRITON_EXPORT
void clear(
void);
293 TRITON_EXPORT
void setThumb(
bool state);
This interface is used as abstract CPU interface. All CPU must use this interface.
This class is used to represent an instruction.
This class is used to represent a memory access.
This class is used when an instruction has a register operand.
This class is used to describe the x86 (32-bits) spec.
triton::uint8 cr5[triton::size::dword]
Concrete value of cr5.
triton::uint8 dr2[triton::size::dword]
Condete value of dr2.
triton::uint8 dr1[triton::size::dword]
Condete value of dr1.
triton::uint8 efer[triton::size::qword]
Concrete value of the EFER MSR Register.
triton::uint8 st1[triton::size::fword]
Concrete value of st1.
triton::uint8 dr7[triton::size::dword]
Condete value of dr7.
triton::uint8 tsc[triton::size::qword]
Concrete value of the TSC Register.
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
triton::uint8 gs[triton::size::dword]
Concrete value of GS.
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register ®, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
TRITON_EXPORT bool isSTX(triton::arch::register_e regId) const
Returns true if regId is a STX register.
triton::uint8 dr3[triton::size::dword]
Condete value of dr3.
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
virtual TRITON_EXPORT ~x86Cpu()
Destructor.
triton::uint8 cr9[triton::size::dword]
Concrete value of cr9.
triton::uint8 mxcsr[triton::size::dword]
Concrete value of the SSE Register State.
triton::uint8 st7[triton::size::fword]
Concrete value of st7.
triton::uint8 fds[triton::size::word]
Concrete value of the x87 FPU Instruction Operand Pointer Selector.
triton::uint8 ebx[triton::size::dword]
Concrete value of ebx.
triton::uint8 fdp[triton::size::qword]
Concrete value of the x87 FPU Instruction Operand Pointer Offset.
triton::uint8 st6[triton::size::fword]
Concrete value of st6.
TRITON_EXPORT bool isSegment(triton::arch::register_e regId) const
Returns true if regId is a Segment.
TRITON_EXPORT x86Cpu(triton::callbacks::Callbacks *callbacks=nullptr)
Constructor.
TRITON_EXPORT bool isEFER(triton::arch::register_e regId) const
Returns true if regId is an EFER register.
triton::uint8 st4[triton::size::fword]
Concrete value of st4.
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
triton::uint8 fop[triton::size::word]
Concrete value of the x87 FPU Opcode.
triton::uint8 cr7[triton::size::dword]
Concrete value of cr7.
triton::uint8 ebp[triton::size::dword]
Concrete value of ebp.
TRITON_EXPORT bool isAVX256(triton::arch::register_e regId) const
Returns true if regId is a AVX-256 (YMM) register.
triton::uint8 ymm3[triton::size::qqword]
Concrete value of ymm3.
triton::uint8 cr13[triton::size::dword]
Concrete value of cr13.
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
TRITON_EXPORT bool isControl(triton::arch::register_e regId) const
Returns true if regId is a control (cr) register.
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
triton::uint8 ftw[triton::size::word]
Concrete value of the x87 FPU Tag Word.
triton::uint8 fcw[triton::size::word]
Concrete value of the x87 FPU Control Word.
TRITON_EXPORT bool isSSE(triton::arch::register_e regId) const
Returns true if regId is a SSE register.
triton::uint8 st5[triton::size::fword]
Concrete value of st5.
triton::uint8 fsw[triton::size::word]
Concrete value of the x87 FPU Status Word.
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
triton::uint8 ymm4[triton::size::qqword]
Concrete value of ymm4.
triton::uint8 ymm7[triton::size::qqword]
Concrete value of ymm7.
triton::uint8 cs[triton::size::dword]
Concrete value of CS.
TRITON_EXPORT x86Cpu & operator=(const x86Cpu &other)
Copies a x86Cpu class.
triton::uint8 esi[triton::size::dword]
Concrete value of esi.
triton::uint8 ds[triton::size::dword]
Concrete value of DS.
TRITON_EXPORT bool isTSC(triton::arch::register_e regId) const
Returns true if regId is an TSC register.
triton::uint8 mxcsr_mask[triton::size::dword]
Concrete value of the SSE Register State Mask.
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
triton::uint8 ymm0[triton::size::qqword]
Concrete value of ymm0.
triton::uint8 edi[triton::size::dword]
Concrete value of edi.
triton::uint8 cr4[triton::size::dword]
Concrete value of cr4.
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
triton::uint8 fcs[triton::size::word]
Concrete value of the x87 FPU Instruction Pointer Selector.
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
triton::uint8 ss[triton::size::dword]
Concrete value of SS.
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register ®) const
Returns parent register from a given one.
triton::uint8 es[triton::size::dword]
Concrete value of ES.
triton::uint8 st2[triton::size::fword]
Concrete value of st2.
triton::uint8 eax[triton::size::dword]
Concrete value of eax.
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
triton::uint8 dr0[triton::size::dword]
Concrete value of dr0.
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register ®, bool execCallbacks=true) const
Returns the concrete value of a register.
TRITON_EXPORT bool isSSECTL(triton::arch::register_e regId) const
Returns true if regId is a SSE Contol register.
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
triton::uint8 esp[triton::size::dword]
Concrete value of esp.
triton::uint8 st3[triton::size::fword]
Concrete value of st3.
triton::uint8 st0[triton::size::fword]
Concrete value of st0.
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
triton::uint8 ymm5[triton::size::qqword]
Concrete value of ymm5.
triton::uint8 cr1[triton::size::dword]
Concrete value of cr1.
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
triton::uint8 ymm6[triton::size::qqword]
Concrete value of ymm6.
triton::uint8 eip[triton::size::dword]
Concrete value of eip.
triton::uint8 ecx[triton::size::dword]
Concrete value of ecx.
triton::uint8 dr6[triton::size::dword]
Condete value of dr6.
triton::uint8 cr15[triton::size::dword]
Concrete value of cr15.
triton::uint8 cr11[triton::size::dword]
Concrete value of cr11.
triton::uint8 fs[triton::size::dword]
Concrete value of FS.
triton::uint8 ymm1[triton::size::qqword]
Concrete value of ymm1.
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
triton::uint8 cr2[triton::size::dword]
Concrete value of cr2.
TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const
Returns true if regId is a FPU register.
triton::uint8 cr8[triton::size::dword]
Concrete value of cr8.
TRITON_EXPORT bool isDebug(triton::arch::register_e regId) const
Returns true if regId is a debug (dr) register.
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
triton::uint8 fip[triton::size::qword]
Concrete value of the x87 FPU Instruction Pointer Offset.
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
TRITON_EXPORT bool isMMX(triton::arch::register_e regId) const
Returns true if regId is a MMX register.
triton::uint8 cr10[triton::size::dword]
Concrete value of cr10.
triton::uint8 ymm2[triton::size::qqword]
Concrete value of ymm2.
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
triton::uint8 cr14[triton::size::dword]
Concrete value of cr14.
triton::uint8 cr12[triton::size::dword]
Concrete value of cr12.
triton::uint8 cr0[triton::size::dword]
Concrete value of cr0.
triton::uint8 cr6[triton::size::dword]
Concrete value of cr6.
triton::uint8 cr3[triton::size::dword]
Concrete value of cr3.
triton::uint8 eflags[triton::size::dword]
Concrete value of eflags.
triton::uint8 edx[triton::size::dword]
Concrete value of edx.
The x86Specifications class defines specifications about the x86 and x86_64 CPU.
register_e
Types of register.
constexpr triton::uint32 fword
fword size in byte
constexpr triton::uint32 dword
dword size in byte
constexpr triton::uint32 word
word size in byte
constexpr triton::uint32 qword
qword size in byte
constexpr triton::uint32 qqword
qqword size in byte
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits