libTriton version 1.0 build 1592
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3** Copyright (C) - Triton
5** This program is under the terms of the Apache License 2.0.
8#ifndef TRITON_X8664CPU_HPP
9#define TRITON_X8664CPU_HPP
11#include <set>
12#include <string>
13#include <unordered_map>
14#include <vector>
16#include <triton/archEnums.hpp>
17#include <triton/callbacks.hpp>
19#include <triton/dllexport.hpp>
22#include <triton/register.hpp>
29namespace triton {
36 namespace arch {
44 namespace x86 {
53 class x8664Cpu : public CpuInterface, public x86Specifications {
55 static const triton::arch::register_e pcId = triton::arch::ID_REG_X86_RIP;
56 static const triton::arch::register_e spId = triton::arch::ID_REG_X86_RSP;
58 private:
63 std::size_t handle;
66 void copy(const x8664Cpu& other);
69 void disassInit(void);
71 protected:
79 std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>> memory;
278 public:
280 TRITON_EXPORT x8664Cpu(triton::callbacks::Callbacks* callbacks=nullptr);
283 TRITON_EXPORT x8664Cpu(const x8664Cpu& other);
286 TRITON_EXPORT virtual ~x8664Cpu();
289 TRITON_EXPORT x8664Cpu& operator=(const x8664Cpu& other);
292 TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const;
295 TRITON_EXPORT bool isMMX(triton::arch::register_e regId) const;
298 TRITON_EXPORT bool isSTX(triton::arch::register_e regId) const;
301 TRITON_EXPORT bool isSSECTL(triton::arch::register_e regId) const;
304 TRITON_EXPORT bool isSSE(triton::arch::register_e regId) const;
307 TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const;
310 TRITON_EXPORT bool isEFER(triton::arch::register_e regId) const;
313 TRITON_EXPORT bool isTSC(triton::arch::register_e regId) const;
316 TRITON_EXPORT bool isAVX256(triton::arch::register_e regId) const;
319 TRITON_EXPORT bool isAVX512(triton::arch::register_e regId) const;
322 TRITON_EXPORT bool isAVX512Parent(triton::arch::register_e regId) const;
325 TRITON_EXPORT bool isControl(triton::arch::register_e regId) const;
328 TRITON_EXPORT bool isDebug(triton::arch::register_e regId) const;
331 TRITON_EXPORT bool isSegment(triton::arch::register_e regId) const;
333 /* Virtual pure inheritance ================================================= */
334 TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const;
335 TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const;
336 TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const;
337 TRITON_EXPORT bool isThumb(void) const;
338 TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess& mem) const;
339 TRITON_EXPORT const std::unordered_map<triton::arch::register_e, const triton::arch::Register>& getAllRegisters(void) const;
340 TRITON_EXPORT const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>& getConcreteMemory(void) const;
341 TRITON_EXPORT const triton::arch::Register& getParentRegister(const triton::arch::Register& reg) const;
343 TRITON_EXPORT const triton::arch::Register& getProgramCounter(void) const;
344 TRITON_EXPORT const triton::arch::Register& getRegister(triton::arch::register_e id) const;
345 TRITON_EXPORT const triton::arch::Register& getRegister(const std::string& name) const;
346 TRITON_EXPORT const triton::arch::Register& getStackPointer(void) const;
347 TRITON_EXPORT std::set<const triton::arch::Register*> getParentRegisters(void) const;
348 TRITON_EXPORT std::vector<triton::uint8> getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const;
349 TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const;
350 TRITON_EXPORT triton::uint32 gprBitSize(void) const;
351 TRITON_EXPORT triton::uint32 gprSize(void) const;
352 TRITON_EXPORT triton::uint32 numberOfRegisters(void) const;
353 TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess& mem, bool execCallbacks=true) const;
354 TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register& reg, bool execCallbacks=true) const;
355 TRITON_EXPORT triton::uint8 getConcreteMemoryValue(triton::uint64 addr, bool execCallbacks=true) const;
356 TRITON_EXPORT void clear(void);
357 TRITON_EXPORT void disassembly(triton::arch::Instruction& inst);
358 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector<triton::uint8>& values, bool execCallbacks=true);
359 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const void* area, triton::usize size, bool execCallbacks=true);
360 TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess& mem, const triton::uint512& value, bool execCallbacks=true);
361 TRITON_EXPORT void setConcreteMemoryValue(triton::uint64 addr, triton::uint8 value, bool execCallbacks=true);
362 TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register& reg, const triton::uint512& value, bool execCallbacks=true);
363 TRITON_EXPORT void setThumb(bool state);
364 TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess& mem, bool tag);
365 TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess& mem) const;
366 TRITON_EXPORT bool isConcreteMemoryValueDefined(triton::uint64 baseAddr, triton::usize size=1) const;
367 TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess& mem);
368 TRITON_EXPORT void clearConcreteMemoryValue(triton::uint64 baseAddr, triton::usize size=1);
369 /* End of virtual pure inheritance ========================================== */
370 };
373 };
375 };
379#endif /* TRITON_X8664CPU_HPP */
This interface is used as abstract CPU interface. All CPU must use this interface.
This class is used to represent an instruction.
This class is used to represent a memory access.
This class is used when an instruction has a register operand.
Definition register.hpp:44
This class is used to describe the x86 (64-bits) spec.
Definition x8664Cpu.hpp:53
triton::uint8 gs[triton::size::qword]
Concrete value of GS.
Definition x8664Cpu.hpp:238
triton::uint8 zmm0[triton::size::dqqword]
Concrete value of zmm0.
Definition x8664Cpu.hpp:134
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
Definition x8664Cpu.cpp:295
triton::uint8 zmm18[triton::size::dqqword]
Concrete value of zmm18.
Definition x8664Cpu.hpp:170
triton::uint8 cr12[triton::size::qword]
Concrete value of cr12.
Definition x8664Cpu.hpp:222
triton::uint8 rax[triton::size::qword]
Concrete value of rax.
Definition x8664Cpu.hpp:82
TRITON_EXPORT x8664Cpu & operator=(const x8664Cpu &other)
Copies a x8664Cpu class.
Definition x8664Cpu.cpp:272
triton::uint8 dr7[triton::size::qword]
Condete value of dr7.
Definition x8664Cpu.hpp:252
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
Definition x8664Cpu.cpp:391
triton::uint8 st4[triton::size::fword]
Concrete value of st4.
Definition x8664Cpu.hpp:126
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
triton::uint8 zmm30[triton::size::dqqword]
Concrete value of zmm30.
Definition x8664Cpu.hpp:194
triton::uint8 es[triton::size::qword]
Concrete value of ES.
Definition x8664Cpu.hpp:234
triton::uint8 zmm10[triton::size::dqqword]
Concrete value of zmm10.
Definition x8664Cpu.hpp:154
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register &reg, bool execCallbacks=true) const
Returns the concrete value of a register.
Definition x8664Cpu.cpp:669
triton::uint8 r10[triton::size::qword]
Concrete value of r10.
Definition x8664Cpu.hpp:104
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
Definition x8664Cpu.cpp:410
triton::uint8 zmm12[triton::size::dqqword]
Concrete value of zmm12.
Definition x8664Cpu.hpp:158
triton::uint8 cr1[triton::size::qword]
Concrete value of cr1.
Definition x8664Cpu.hpp:200
triton::uint8 st1[triton::size::fword]
Concrete value of st1.
Definition x8664Cpu.hpp:120
triton::uint8 zmm21[triton::size::dqqword]
Concrete value of zmm21.
Definition x8664Cpu.hpp:176
triton::uint8 r12[triton::size::qword]
Concrete value of r12.
Definition x8664Cpu.hpp:108
triton::uint8 cr10[triton::size::qword]
Concrete value of cr10.
Definition x8664Cpu.hpp:218
triton::uint8 eflags[triton::size::qword]
Concrete value of eflags.
Definition x8664Cpu.hpp:116
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
Definition x8664Cpu.cpp:500
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
triton::uint8 zmm5[triton::size::dqqword]
Concrete value of zmm5.
Definition x8664Cpu.hpp:144
TRITON_EXPORT bool isSSECTL(triton::arch::register_e regId) const
Returns true if regId is a SSE Contol register.
Definition x8664Cpu.cpp:334
TRITON_EXPORT bool isAVX512Parent(triton::arch::register_e regId) const
Returns true if regId is a AVX-512 (ZMM) register.
Definition x8664Cpu.cpp:372
TRITON_EXPORT x8664Cpu(triton::callbacks::Callbacks *callbacks=nullptr)
Definition x8664Cpu.cpp:26
triton::uint8 cr7[triton::size::qword]
Concrete value of cr7.
Definition x8664Cpu.hpp:212
triton::uint8 zmm7[triton::size::dqqword]
Concrete value of zmm7.
Definition x8664Cpu.hpp:148
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
Definition x8664Cpu.cpp:638
triton::uint8 zmm9[triton::size::dqqword]
Concrete value of zmm9.
Definition x8664Cpu.hpp:152
triton::uint8 zmm2[triton::size::dqqword]
Concrete value of zmm2.
Definition x8664Cpu.hpp:138
triton::uint8 dr1[triton::size::qword]
Condete value of dr1.
Definition x8664Cpu.hpp:244
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
Definition x8664Cpu.cpp:470
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
Definition x8664Cpu.hpp:79
triton::uint8 zmm27[triton::size::dqqword]
Concrete value of zmm27.
Definition x8664Cpu.hpp:188
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
Definition x8664Cpu.cpp:406
triton::uint8 mxcsr_mask[triton::size::dword]
Concrete value of the SSE Register State Mask.
Definition x8664Cpu.hpp:274
triton::uint8 rip[triton::size::qword]
Concrete value of rip.
Definition x8664Cpu.hpp:98
triton::uint8 zmm16[triton::size::dqqword]
Concrete value of zmm16.
Definition x8664Cpu.hpp:166
TRITON_EXPORT bool isAVX256(triton::arch::register_e regId) const
Returns true if regId is a AVX-256 (YMM) register.
Definition x8664Cpu.cpp:359
TRITON_EXPORT bool isEFER(triton::arch::register_e regId) const
Returns true if regId is an EFER register.
Definition x8664Cpu.cpp:349
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
Definition x8664Cpu.cpp:415
triton::uint8 zmm20[triton::size::dqqword]
Concrete value of zmm20.
Definition x8664Cpu.hpp:174
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
TRITON_EXPORT bool isMMX(triton::arch::register_e regId) const
Returns true if regId is a MMX register.
Definition x8664Cpu.cpp:324
triton::uint8 dr6[triton::size::qword]
Condete value of dr6.
Definition x8664Cpu.hpp:250
triton::uint8 cr13[triton::size::qword]
Concrete value of cr13.
Definition x8664Cpu.hpp:224
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
Definition x8664Cpu.cpp:659
triton::uint8 fdp[triton::size::qword]
Concrete value of the x87 FPU Instruction Operand Pointer Offset.
Definition x8664Cpu.hpp:266
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
Definition x8664Cpu.cpp:396
triton::uint8 cr14[triton::size::qword]
Concrete value of cr14.
Definition x8664Cpu.hpp:226
triton::uint8 st5[triton::size::fword]
Concrete value of st5.
Definition x8664Cpu.hpp:128
triton::uint8 zmm6[triton::size::dqqword]
Concrete value of zmm6.
Definition x8664Cpu.hpp:146
triton::uint8 cr2[triton::size::qword]
Concrete value of cr2.
Definition x8664Cpu.hpp:202
triton::uint8 cr11[triton::size::qword]
Concrete value of cr11.
Definition x8664Cpu.hpp:220
triton::uint8 cr4[triton::size::qword]
Concrete value of cr4.
Definition x8664Cpu.hpp:206
TRITON_EXPORT bool isSSE(triton::arch::register_e regId) const
Returns true if regId is a SSE register.
Definition x8664Cpu.cpp:339
triton::uint8 cr8[triton::size::qword]
Concrete value of cr8.
Definition x8664Cpu.hpp:214
triton::uint8 dr0[triton::size::qword]
Concrete value of dr0.
Definition x8664Cpu.hpp:242
triton::uint8 zmm13[triton::size::dqqword]
Concrete value of zmm13.
Definition x8664Cpu.hpp:160
triton::uint8 cr9[triton::size::qword]
Concrete value of cr9.
Definition x8664Cpu.hpp:216
triton::uint8 st7[triton::size::fword]
Concrete value of st7.
Definition x8664Cpu.hpp:132
triton::uint8 fcw[triton::size::word]
Concrete value of the x87 FPU Control Word.
Definition x8664Cpu.hpp:254
triton::uint8 zmm8[triton::size::dqqword]
Concrete value of zmm8.
Definition x8664Cpu.hpp:150
triton::uint8 efer[triton::size::qword]
Concrete value of the EFER MSR Register.
Definition x8664Cpu.hpp:270
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
triton::uint8 zmm22[triton::size::dqqword]
Concrete value of zmm22.
Definition x8664Cpu.hpp:178
triton::uint8 ss[triton::size::qword]
Concrete value of SS.
Definition x8664Cpu.hpp:240
triton::uint8 r9[triton::size::qword]
Concrete value of r9.
Definition x8664Cpu.hpp:102
triton::uint8 rdx[triton::size::qword]
Concrete value of rdx.
Definition x8664Cpu.hpp:88
triton::uint8 mxcsr[triton::size::dword]
Concrete value of the SSE Register State.
Definition x8664Cpu.hpp:272
triton::uint8 cr0[triton::size::qword]
Concrete value of cr0.
Definition x8664Cpu.hpp:198
triton::uint8 r15[triton::size::qword]
Concrete value of r15.
Definition x8664Cpu.hpp:114
triton::uint8 dr3[triton::size::qword]
Condete value of dr3.
Definition x8664Cpu.hpp:248
triton::uint8 rsi[triton::size::qword]
Concrete value of rsi.
Definition x8664Cpu.hpp:92
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
triton::uint8 fs[triton::size::qword]
Concrete value of FS.
Definition x8664Cpu.hpp:236
triton::uint8 r11[triton::size::qword]
Concrete value of r11.
Definition x8664Cpu.hpp:106
TRITON_EXPORT bool isControl(triton::arch::register_e regId) const
Returns true if regId is a control (cr) register.
Definition x8664Cpu.cpp:376
triton::uint8 cr5[triton::size::qword]
Concrete value of cr5.
Definition x8664Cpu.hpp:208
TRITON_EXPORT bool isAVX512(triton::arch::register_e regId) const
Returns true if regId is a AVX-512 (ZMM) register, or XMM and YMM registers after 15.
Definition x8664Cpu.cpp:364
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
Definition x8664Cpu.cpp:401
triton::uint8 fcs[triton::size::word]
Concrete value of the x87 FPU Instruction Pointer Selector.
Definition x8664Cpu.hpp:264
triton::uint8 fop[triton::size::word]
Concrete value of the x87 FPU Opcode.
Definition x8664Cpu.hpp:260
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
Definition x8664Cpu.cpp:283
triton::uint8 zmm29[triton::size::dqqword]
Concrete value of zmm29.
Definition x8664Cpu.hpp:192
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
Definition x8664Cpu.cpp:510
triton::uint8 zmm31[triton::size::dqqword]
Concrete value of zmm31.
Definition x8664Cpu.hpp:196
triton::uint8 rbx[triton::size::qword]
Concrete value of rbx.
Definition x8664Cpu.hpp:84
triton::uint8 zmm4[triton::size::dqqword]
Concrete value of zmm4.
Definition x8664Cpu.hpp:142
TRITON_EXPORT bool isSegment(triton::arch::register_e regId) const
Returns true if regId is a Segment.
Definition x8664Cpu.cpp:386
triton::uint8 zmm3[triton::size::dqqword]
Concrete value of zmm3.
Definition x8664Cpu.hpp:140
triton::uint8 fds[triton::size::word]
Concrete value of the x87 FPU Instruction Operand Pointer Selector.
Definition x8664Cpu.hpp:268
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register &reg) const
Returns parent register from a given one.
Definition x8664Cpu.cpp:490
triton::uint8 zmm14[triton::size::dqqword]
Concrete value of zmm14.
Definition x8664Cpu.hpp:162
triton::uint8 r8[triton::size::qword]
Concrete value of r8.
Definition x8664Cpu.hpp:100
triton::uint8 rdi[triton::size::qword]
Concrete value of rdi.
Definition x8664Cpu.hpp:90
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
Definition x8664Cpu.cpp:319
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
Definition x8664Cpu.cpp:505
triton::uint8 st0[triton::size::fword]
Concrete value of st0.
Definition x8664Cpu.hpp:118
triton::uint8 zmm24[triton::size::dqqword]
Concrete value of zmm24.
Definition x8664Cpu.hpp:182
virtual TRITON_EXPORT ~x8664Cpu()
Definition x8664Cpu.cpp:40
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
triton::uint8 r14[triton::size::qword]
Concrete value of r14.
Definition x8664Cpu.hpp:112
triton::uint8 tsc[triton::size::qword]
Concrete value of the TSC Register.
Definition x8664Cpu.hpp:276
triton::uint8 cr3[triton::size::qword]
Concrete value of cr3.
Definition x8664Cpu.hpp:204
triton::uint8 zmm1[triton::size::dqqword]
Concrete value of zmm1.
Definition x8664Cpu.hpp:136
triton::uint8 zmm28[triton::size::dqqword]
Concrete value of zmm28.
Definition x8664Cpu.hpp:190
triton::uint8 ds[triton::size::qword]
Concrete value of DS.
Definition x8664Cpu.hpp:232
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
triton::uint8 zmm23[triton::size::dqqword]
Concrete value of zmm23.
Definition x8664Cpu.hpp:180
triton::uint8 st6[triton::size::fword]
Concrete value of st6.
Definition x8664Cpu.hpp:130
triton::uint8 zmm19[triton::size::dqqword]
Concrete value of zmm19.
Definition x8664Cpu.hpp:172
triton::uint8 rbp[triton::size::qword]
Concrete value of rbp.
Definition x8664Cpu.hpp:94
triton::uint8 zmm11[triton::size::dqqword]
Concrete value of zmm11.
Definition x8664Cpu.hpp:156
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
Definition x8664Cpu.cpp:278
triton::uint8 rcx[triton::size::qword]
Concrete value of rcx.
Definition x8664Cpu.hpp:86
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
triton::uint8 st3[triton::size::fword]
Concrete value of st3.
Definition x8664Cpu.hpp:124
triton::uint8 fsw[triton::size::word]
Concrete value of the x87 FPU Status Word.
Definition x8664Cpu.hpp:256
triton::uint8 r13[triton::size::qword]
Concrete value of r13.
Definition x8664Cpu.hpp:110
triton::uint8 cr6[triton::size::qword]
Concrete value of cr6.
Definition x8664Cpu.hpp:210
triton::uint8 dr2[triton::size::qword]
Condete value of dr2.
Definition x8664Cpu.hpp:246
TRITON_EXPORT bool isFPU(triton::arch::register_e regId) const
Returns true if regId is a FPU register.
Definition x8664Cpu.cpp:344
triton::uint8 cr15[triton::size::qword]
Concrete value of cr15.
Definition x8664Cpu.hpp:228
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
Definition x8664Cpu.cpp:314
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
Definition x8664Cpu.cpp:166
triton::uint8 fip[triton::size::qword]
Concrete value of the x87 FPU Instruction Pointer Offset.
Definition x8664Cpu.hpp:262
triton::uint8 zmm26[triton::size::dqqword]
Concrete value of zmm26.
Definition x8664Cpu.hpp:186
triton::uint8 rsp[triton::size::qword]
Concrete value of rsp.
Definition x8664Cpu.hpp:96
TRITON_EXPORT bool isSTX(triton::arch::register_e regId) const
Returns true if regId is a STX register.
Definition x8664Cpu.cpp:329
triton::uint8 zmm25[triton::size::dqqword]
Concrete value of zmm25.
Definition x8664Cpu.hpp:184
triton::uint8 st2[triton::size::fword]
Concrete value of st2.
Definition x8664Cpu.hpp:122
triton::uint8 zmm15[triton::size::dqqword]
Concrete value of zmm15.
Definition x8664Cpu.hpp:164
triton::uint8 ftw[triton::size::word]
Concrete value of the x87 FPU Tag Word.
Definition x8664Cpu.hpp:258
TRITON_EXPORT bool isTSC(triton::arch::register_e regId) const
Returns true if regId is an TSC register.
Definition x8664Cpu.cpp:354
triton::uint8 zmm17[triton::size::dqqword]
Concrete value of zmm17.
Definition x8664Cpu.hpp:168
TRITON_EXPORT bool isDebug(triton::arch::register_e regId) const
Returns true if regId is a debug (dr) register.
Definition x8664Cpu.cpp:381
triton::uint8 cs[triton::size::qword]
Concrete value of CS.
Definition x8664Cpu.hpp:230
The x86Specifications class defines specifications about the x86 and x86_64 CPU.
The callbacks class.
Definition callbacks.hpp:79
Types of register.
Definition archEnums.hpp:64
constexpr triton::uint32 fword
fword size in byte
Definition cpuSize.hpp:38
constexpr triton::uint32 dword
dword size in byte
Definition cpuSize.hpp:34
constexpr triton::uint32 dqqword
dqqword size in byte
Definition cpuSize.hpp:44
constexpr triton::uint32 word
word size in byte
Definition cpuSize.hpp:32
constexpr triton::uint32 qword
qword size in byte
Definition cpuSize.hpp:36
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits
The Triton namespace.