libTriton version 1.0 build 1590
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3** Copyright (C) - Triton
5** This program is under the terms of the Apache License 2.0.
11#include <set>
12#include <string>
13#include <unordered_map>
14#include <vector>
17#include <triton/archEnums.hpp>
18#include <triton/callbacks.hpp>
20#include <triton/dllexport.hpp>
23#include <triton/register.hpp>
29namespace triton {
36 namespace arch {
44 namespace arm {
52 namespace aarch64 {
63 static const triton::arch::register_e pcId = triton::arch::ID_REG_AARCH64_PC;
64 static const triton::arch::register_e spId = triton::arch::ID_REG_AARCH64_SP;
66 private:
71 std::set<triton::uint64> exclusiveMemoryTags;
74 std::size_t handle;
77 void copy(const AArch64Cpu& other);
80 inline void disassInit(void);
82 protected:
90 std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>> memory;
226 #define SYS_REG_SPEC(_, LOWER_NAME, _2, _3, _4, _5) \
227 triton::uint8 LOWER_NAME[triton::size::qword];
228 #define REG_SPEC(_1, _2, _3, _4, _5, _6)
229 #define REG_SPEC_NO_CAPSTONE(_1, _2, _3, _4, _5, _6)
230 #include "triton/aarch64.spec"
232 public:
234 TRITON_EXPORT AArch64Cpu(triton::callbacks::Callbacks* callbacks=nullptr);
237 TRITON_EXPORT AArch64Cpu(const AArch64Cpu& other);
240 TRITON_EXPORT virtual ~AArch64Cpu();
243 TRITON_EXPORT AArch64Cpu& operator=(const AArch64Cpu& other);
246 TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const;
249 TRITON_EXPORT bool isScalarRegister(triton::arch::register_e regId) const;
252 TRITON_EXPORT bool isVectorRegister(triton::arch::register_e regId) const;
255 TRITON_EXPORT bool isSystemRegister(triton::arch::register_e regId) const;
257 /* Virtual pure inheritance ================================================= */
258 TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const;
259 TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const;
260 TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const;
261 TRITON_EXPORT bool isThumb(void) const;
262 TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess& mem) const;
263 TRITON_EXPORT const std::unordered_map<triton::arch::register_e, const triton::arch::Register>& getAllRegisters(void) const;
264 TRITON_EXPORT const std::unordered_map<triton::uint64, triton::uint8, IdentityHash<triton::uint64>>& getConcreteMemory(void) const;
265 TRITON_EXPORT const triton::arch::Register& getParentRegister(const triton::arch::Register& reg) const;
267 TRITON_EXPORT const triton::arch::Register& getProgramCounter(void) const;
268 TRITON_EXPORT const triton::arch::Register& getRegister(triton::arch::register_e id) const;
269 TRITON_EXPORT const triton::arch::Register& getRegister(const std::string& name) const;
270 TRITON_EXPORT const triton::arch::Register& getStackPointer(void) const;
271 TRITON_EXPORT std::set<const triton::arch::Register*> getParentRegisters(void) const;
272 TRITON_EXPORT std::vector<triton::uint8> getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const;
273 TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const;
274 TRITON_EXPORT triton::uint32 gprBitSize(void) const;
275 TRITON_EXPORT triton::uint32 gprSize(void) const;
276 TRITON_EXPORT triton::uint32 numberOfRegisters(void) const;
277 TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess& mem, bool execCallbacks=true) const;
278 TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register& reg, bool execCallbacks=true) const;
279 TRITON_EXPORT triton::uint8 getConcreteMemoryValue(triton::uint64 addr, bool execCallbacks=true) const;
280 TRITON_EXPORT void clear(void);
281 TRITON_EXPORT void disassembly(triton::arch::Instruction& inst);
282 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector<triton::uint8>& values, bool execCallbacks=true);
283 TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const void* area, triton::usize size, bool execCallbacks=true);
284 TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess& mem, const triton::uint512& value, bool execCallbacks=true);
285 TRITON_EXPORT void setConcreteMemoryValue(triton::uint64 addr, triton::uint8 value, bool execCallbacks=true);
286 TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register& reg, const triton::uint512& value, bool execCallbacks=true);
287 TRITON_EXPORT void setThumb(bool state);
288 TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess& mem, bool tag);
289 TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess& mem) const;
290 TRITON_EXPORT bool isConcreteMemoryValueDefined(triton::uint64 baseAddr, triton::usize size=1) const;
291 TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess& mem);
292 TRITON_EXPORT void clearConcreteMemoryValue(triton::uint64 baseAddr, triton::usize size=1);
293 /* End of virtual pure inheritance ========================================== */
294 };
297 };
299 };
301 };
305#endif /* TRITON_AARCH64CPU_HPP */
This interface is used as abstract CPU interface. All CPU must use this interface.
This class is used to represent an instruction.
This class is used to represent a memory access.
This class is used when an instruction has a register operand.
Definition register.hpp:44
This class is used to describe the ARM (64-bits) spec.
triton::uint8 q30[triton::size::dqword]
Concrete value of q30.
triton::uint8 q9[triton::size::dqword]
Concrete value of q9.
TRITON_EXPORT std::vector< triton::uint8 > getConcreteMemoryAreaValue(triton::uint64 baseAddr, triton::usize size, bool execCallbacks=true) const
Returns the concrete value of a memory area.
triton::uint8 x11[triton::size::qword]
Concrete value of x11.
TRITON_EXPORT void clear(void)
Clears the architecture states (registers and memory).
TRITON_EXPORT void setConcreteRegisterValue(const triton::arch::Register &reg, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a register.
triton::uint8 x28[triton::size::qword]
Concrete value of x28.
triton::uint8 x23[triton::size::qword]
Concrete value of x23.
TRITON_EXPORT void clearConcreteMemoryValue(const triton::arch::MemoryAccess &mem)
Clears concrete values assigned to the memory cells.
triton::uint8 x3[triton::size::qword]
Concrete value of x3.
TRITON_EXPORT bool isVectorRegister(triton::arch::register_e regId) const
Returns true if regId is a vector register.
triton::uint8 x29[triton::size::qword]
Concrete value of x29.
TRITON_EXPORT triton::uint32 numberOfRegisters(void) const
Returns the number of registers according to the CPU architecture.
triton::uint8 x2[triton::size::qword]
Concrete value of x2.
triton::uint8 q4[triton::size::dqword]
Concrete value of q4.
triton::uint8 x20[triton::size::qword]
Concrete value of x20.
triton::uint8 x18[triton::size::qword]
Concrete value of x18.
triton::uint8 q29[triton::size::dqword]
Concrete value of q29.
TRITON_EXPORT bool isRegisterValid(triton::arch::register_e regId) const
Returns true if the register ID is valid.
triton::uint8 x8[triton::size::qword]
Concrete value of x8.
TRITON_EXPORT const triton::arch::Register & getStackPointer(void) const
Returns the stack pointer register.
triton::uint8 q14[triton::size::dqword]
Concrete value of q14.
triton::uint8 x10[triton::size::qword]
Concrete value of x10.
TRITON_EXPORT AArch64Cpu & operator=(const AArch64Cpu &other)
Copies a AArch64Cpu class.
triton::uint8 x27[triton::size::qword]
Concrete value of x27.
triton::uint8 q12[triton::size::dqword]
Concrete value of q12.
TRITON_EXPORT bool isSystemRegister(triton::arch::register_e regId) const
Returns true if regId is a system register.
TRITON_EXPORT const std::unordered_map< triton::arch::register_e, const triton::arch::Register > & getAllRegisters(void) const
Returns all registers.
TRITON_EXPORT triton::uint512 getConcreteMemoryValue(const triton::arch::MemoryAccess &mem, bool execCallbacks=true) const
Returns the concrete value of memory cells.
triton::uint8 q27[triton::size::dqword]
Concrete value of q27.
TRITON_EXPORT const triton::arch::Register & getProgramCounter(void) const
Returns the program counter register.
triton::uint8 x30[triton::size::qword]
Concrete value of x30.
triton::uint8 q28[triton::size::dqword]
Concrete value of q28.
TRITON_EXPORT bool isMemoryExclusive(const triton::arch::MemoryAccess &mem) const
Returns true if the given memory access is tagged as exclusive. Only valid for Arm32 and AArch64.
triton::uint8 q1[triton::size::dqword]
Concrete value of q1.
TRITON_EXPORT std::set< const triton::arch::Register * > getParentRegisters(void) const
Returns all parent registers.
triton::uint8 x1[triton::size::qword]
Concrete value of x1.
TRITON_EXPORT bool isGPR(triton::arch::register_e regId) const
Returns true if regId is a GRP.
triton::uint8 q20[triton::size::dqword]
Concrete value of q20.
triton::uint8 x5[triton::size::qword]
Concrete value of x5.
TRITON_EXPORT void setConcreteMemoryAreaValue(triton::uint64 baseAddr, const std::vector< triton::uint8 > &values, bool execCallbacks=true)
[architecture api] - Sets the concrete value of a memory area.
TRITON_EXPORT bool isRegister(triton::arch::register_e regId) const
Returns true if the register ID is a register.
triton::uint8 q18[triton::size::dqword]
Concrete value of q18.
triton::uint8 q15[triton::size::dqword]
Concrete value of q15.
TRITON_EXPORT const triton::arch::Register & getRegister(triton::arch::register_e id) const
Returns register from id.
TRITON_EXPORT triton::uint32 gprBitSize(void) const
Returns the bit in bit of the General Purpose Registers.
triton::uint8 q10[triton::size::dqword]
Concrete value of q10.
TRITON_EXPORT bool isThumb(void) const
Returns true if the execution mode is Thumb. Only useful for Arm32.
triton::uint8 x0[triton::size::qword]
Concrete value of x0.
triton::uint8 q31[triton::size::dqword]
Concrete value of q31.
triton::uint8 q7[triton::size::dqword]
Concrete value of q7.
TRITON_EXPORT void setThumb(bool state)
Sets CPU state to Thumb mode.
TRITON_EXPORT const triton::arch::Register & getParentRegister(const triton::arch::Register &reg) const
Returns parent register from a given one.
std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > memory
map of address -> concrete value
TRITON_EXPORT bool isConcreteMemoryValueDefined(const triton::arch::MemoryAccess &mem) const
Returns true if memory cells have a defined concrete value.
triton::uint8 q22[triton::size::dqword]
Concrete value of q22.
triton::uint8 x6[triton::size::qword]
Concrete value of x6.
triton::uint8 spsr[triton::size::dword]
Concrete value of spsr.
triton::uint8 sp[triton::size::qword]
Concrete value of sp.
TRITON_EXPORT void disassembly(triton::arch::Instruction &inst)
Disassembles the instruction according to the architecture.
triton::uint8 x12[triton::size::qword]
Concrete value of x12.
triton::uint8 x15[triton::size::qword]
Concrete value of x15.
virtual TRITON_EXPORT ~AArch64Cpu()
triton::uint8 q25[triton::size::dqword]
Concrete value of q25.
triton::uint8 x7[triton::size::qword]
Concrete value of x7.
TRITON_EXPORT triton::uint32 gprSize(void) const
Returns the bit in byte of the General Purpose Registers.
triton::uint8 q0[triton::size::dqword]
Concrete value of q0.
TRITON_EXPORT bool isScalarRegister(triton::arch::register_e regId) const
Returns true if regId is a scalar register.
triton::uint8 q26[triton::size::dqword]
Concrete value of q26.
TRITON_EXPORT void setConcreteMemoryValue(const triton::arch::MemoryAccess &mem, const triton::uint512 &value, bool execCallbacks=true)
[architecture api] - Sets the concrete value of memory cells.
triton::uint8 q17[triton::size::dqword]
Concrete value of q17.
triton::uint8 x26[triton::size::qword]
Concrete value of x26.
triton::uint8 x22[triton::size::qword]
Concrete value of x22.
triton::uint8 q8[triton::size::dqword]
Concrete value of q8.
TRITON_EXPORT bool isFlag(triton::arch::register_e regId) const
Returns true if the register ID is a flag.
triton::uint8 x24[triton::size::qword]
Concrete value of x24.
TRITON_EXPORT triton::arch::endianness_e getEndianness(void) const
Returns the kind of endianness as triton::arch::endianness_e.
triton::uint8 q23[triton::size::dqword]
Concrete value of q23.
triton::uint8 q6[triton::size::dqword]
Concrete value of q6.
triton::uint8 x19[triton::size::qword]
Concrete value of x19.
TRITON_EXPORT triton::uint512 getConcreteRegisterValue(const triton::arch::Register &reg, bool execCallbacks=true) const
Returns the concrete value of a register.
triton::uint8 q13[triton::size::dqword]
Concrete value of q13.
TRITON_EXPORT const std::unordered_map< triton::uint64, triton::uint8, IdentityHash< triton::uint64 > > & getConcreteMemory(void) const
Return all memory.
triton::uint8 q2[triton::size::dqword]
Concrete value of q2.
triton::uint8 x17[triton::size::qword]
Concrete value of x17.
TRITON_EXPORT void setMemoryExclusiveTag(const triton::arch::MemoryAccess &mem, bool tag)
Sets exclusive memory access tag. Only valid for Arm32 and AArch64.
triton::uint8 q21[triton::size::dqword]
Concrete value of q21.
triton::uint8 x9[triton::size::qword]
Concrete value of x9.
triton::uint8 q11[triton::size::dqword]
Concrete value of q11.
triton::uint8 x13[triton::size::qword]
Concrete value of x13.
triton::uint8 x21[triton::size::qword]
Concrete value of x21.
triton::uint8 q3[triton::size::dqword]
Concrete value of q3.
triton::uint8 q5[triton::size::dqword]
Concrete value of q5.
triton::uint8 q19[triton::size::dqword]
Concrete value of q19.
triton::uint8 x14[triton::size::qword]
Concrete value of x14.
triton::uint8 x4[triton::size::qword]
Concrete value of x4.
triton::uint8 x25[triton::size::qword]
Concrete value of x25.
triton::uint8 x16[triton::size::qword]
Concrete value of x16.
triton::uint8 q24[triton::size::dqword]
Concrete value of q24.
triton::uint8 q16[triton::size::dqword]
Concrete value of q16.
triton::uint8 pc[triton::size::qword]
Concrete value of pc.
The AArch64Specifications class defines specifications about the AArch64 CPU.
The callbacks class.
Definition callbacks.hpp:79
Types of register.
Definition archEnums.hpp:64
constexpr triton::uint32 dword
dword size in byte
Definition cpuSize.hpp:34
constexpr triton::uint32 dqword
dqword size in byte
Definition cpuSize.hpp:40
constexpr triton::uint32 qword
qword size in byte
Definition cpuSize.hpp:36
std::size_t usize
unsigned MAX_INT 32 or 64 bits according to the CPU.
std::uint64_t uint64
unisgned 64-bits
math::wide_integer::uint512_t uint512
unsigned 512-bits
std::uint32_t uint32
unisgned 32-bits
std::uint8_t uint8
unisgned 8-bits
The Triton namespace.